Building a Trustworthy Autonomous Vehicle (AV) Architecture

Riccardo Mariani
Senior Functional Safety Architect, NVIDIA

Jyotika Athavale
Senior Functional Safety Architect, NVIDIA

Hardware ASIC / System Safety are key enablers for the overall robustness and dependability of autonomous vehicle architectures. In developing functional safety that addresses hardware random failures and systematic failures, it is also crucial to consider cybersecurity and safety of intended functionality (SOTIF). In this keynote, we’ll cover NVIDIA’s vision for functional safety, as well as our work with various international governing standards and regulations. The talk will also include an overview of the standard IEEE P2851, which aims to provide an exchangeable and interoperable format for safety analysis and safety verification activities at IP, SoC and system levels. The standard addresses interoperability challenges of dependable systems covering functional safety, SOTIF, cybersecurity and other characteristics such as reliability, maintainability and real time.

CNN Acceleration: A Short Road Trip

Filip Moerman
Bosch

Convolutional Neural Networks (CNN) are widely adopted for various computer vision tasks. They are also gaining traction in the auto-motive industry. As such, front-view cameras may rely on CNNs for semantic segmentation and object detection. They typically require very performant and very efficient CNN accelerators. The presentation will give a brief overview of CNNs in general. It will explain the use of CNNs for semantic segmentation and object detection and describe some CNNs designed for these tasks. It will discuss the challenges of embedding a CNN accelerator in a SoC and of providing a SW tool chain that enables the full performance and efficiency of the CNN accelerator. It will describe the performance results generated by Bosch using Synopsys' DesignWare ARC EV processor and CNN engine with 3520 MACs.

Accelerate the Development of Dependable Automotive SoCs with Synopsys’ Comprehensive Safety-Aware Solution

Stewart Williams
Senior Automotive Vertical Marketing Manager, Synopsys

At higher levels of autonomy, the autonomous driving (AD) compute solution will become more centralized to rapidly fuse multimodal sensor data and safely choose and initiate self-driving actions. Complex automotive SoCs with purpose-built processors to increase computational efficiency require automotive-grade IP and ISO 26262-certified safety-aware design and hardware and software verification solutions to meet strict design targets to achieve target ASIL. Before silicon is available, early development and testing of safe and secure software relies on virtualized hardware. Synopsys partners with automotive market leaders and new entrants to accelerate development of safety-critical SoC. In this session, we present Synopsys’ safety-aware expertise, IP and tool solution to help reduce cost, alleviate risk and accelerate go-to-market.

Influence of Dynamic Driving Model on SoC Development and IP Selection

Bernhard Bauer
Product Safety Expert, Synopsys

Engineering an autonomous driving (AD) system requires a thorough understanding of the dynamic interaction between driver, vehicle, and environment. A dynamic model at the driving level enables design of an E/E network architecture with E/E systems as acting nodes which meets the customer expectation. In this presentation we discuss why the success of the SoC design architecture is highly dependent on the dynamic model of the ADAS/AD feature at the driving level. Key requirements include assigning the appropriate sense, control, and actuation functions to the SoC, laying out the SoC function with sufficient performance (SOTIF), avoiding and mitigating random and systematic faults (functional safety), and preventing malevolent intrusion to the SoC and from there into the whole E/E network (security).

Samsung Foundry's Automotive Reference Flow

Eunju Hwang
Samsung Foundry

Automobiles must operate in a safe, reliable and secure manner, especially in next-generation autonomous driving and advanced driver-assistance systems (ADAS) applications. E/E systems in such vehicles, such as SoC designs, should comply with the ISO 26262 standard to achieve functional safety which is specified by automotive safety integrity level (ASIL). Samsung Foundry will present how their automotive reference flow is using Synopsys’s comprehensive automotive solutions that help their customers meet their target ASILs.

Replay: Building a Trustworthy Autonomous Vehicle (AV) Architecture

Riccardo Mariani
Senior Functional Safety Architect, NVIDIA

Jyotika Athavale
Senior Functional Safety Architect, NVIDIA

Hardware ASIC / System Safety are key enablers for the overall robustness and dependability of autonomous vehicle architectures. In developing functional safety that addresses hardware random failures and systematic failures, it is also crucial to consider cybersecurity and safety of intended functionality (SOTIF). In this keynote, we’ll cover NVIDIA’s vision for functional safety, as well as our work with various international governing standards and regulations. The talk will also include an overview of the standard IEEE P2851, which aims to provide an exchangeable and interoperable format for safety analysis and safety verification activities at IP, SoC and system levels. The standard addresses interoperability challenges of dependable systems covering functional safety, SOTIF, cybersecurity and other characteristics such as reliability, maintainability and real time.

Replay: CNN Acceleration: A Short Road Trip

Filip Moerman
Bosch

Convolutional Neural Networks (CNN) are widely adopted for various computer vision tasks. They are also gaining traction in the auto-motive industry. As such, front-view cameras may rely on CNNs for semantic segmentation and object detection. They typically require very performant and very efficient CNN accelerators. The presentation will give a brief overview of CNNs in general. It will explain the use of CNNs for semantic segmentation and object detection and describe some CNNs designed for these tasks. It will discuss the challenges of embedding a CNN accelerator in a SoC and of providing a SW tool chain that enables the full performance and efficiency of the CNN accelerator. It will describe the performance results generated by Bosch using Synopsys' DesignWare ARC EV processor and CNN engine with 3520 MACs.

Replay: Accelerate the Development of Dependable SoCs

Stewart Williams
Senior Automotive Vertical Marketing Manager, Synopsys

Hybrid EDA Workloads in Public Cloud

Anupama Asthana
Vice President, Marketing, Resorts World Genting, Qualcomm

Enabling EDA workloads in public cloud creates flexibility in engineering execution during compute demand peaks by providing the ability for key workloads to run in hybrid cloud mode. Static Timing Analysis is one of the most compute/memory intensive workflow for peak shaving, Qualcomm worked with Synopsys R&D to enable this capability in AWS . Some challenges faced were how STA is complex to execute and reside at tail end of design cycle, leaving little tolerance for delay. In summary, EDA workloads in the cloud have demonstrated equal or better performance in AWS vs. on premises.

*Secure Cloud-Based Lynx Virtual Design Environment Enabling Accurate and Efficient Physical Verification and Fabrication Signoff

Lifu Chang
Director, The MOSIS Service

*User Presentation

Migrating and Executing EDA Workloads on Cloud with Synopsys Testcase Packager

Jishnu Dave
Senior Software Engineer, Synopsys

Synopsys Testcase Packager (STP) is the next generation, application-agnostic, zero-integration testcase packaging technology for all Synopsys Products. EDA environments are highly complex with different dependencies and undergo a high frequency of unregulated changes. STP has significantly improved the productivity by automatically capturing a complete customer testcase and reproducing it in a remote environment. Typically, EDA workloads have large data sizes which makes uploading to Cloud impractical during peak usage e.g. 10,000+ cores. STP solves this with "EDA Data Environment" synchronization. That is, pre-populate and continually auto-synchronize data between on-premises and Cloud for on-demand execution.

Design Processing and Verification Using Kubernetes Based Hybrid Cloud Infrastructure

Clifford Osborn
Senior Engineer, IBM

IBM and Synopsys have been working together to investigate the advantages and trade-offs of migrating high performance EDA applications to the cloud. In this work, we describe the incorporation of synopsys icv validator tools into a digital design flow enabled on a hybrid cloud infrastructure. Large chips require significant compute resource for design and validation of data. Our emphasis in this work is to reduce the process time by running synopsis icv validator applications in kubernetes based containers. Virtual machines are configured with defined cpu and memory requirements. Runtime improvements are realized by taking advantage of icv distributed and multi-threaded capabilities. The advantage of kubernetes is that they can be ported to any cloud environment. We discuss the advantages and disadvantages of running applications using on premis and hybrid cloud models.

Containerization for EDA Workloads

Jagdish Reddy
Engineering Director, Synopsys

We have been investing in technologies to accelerate our product enablement on the public cloud. These include job distribution, scalability, elasticity, data transfer, containerization, and more. We explored containerization as this technology provides many benefits such as isolation from host dependencies, bundling all application dependencies into single package, and lowering the overhead compared to virtual machines. In this talk, we will present our journey in enabling the framework for container support for our products both on-prem and on the cloud with the leading container HPC and native solutions, namely Singularity and Docker.

*Migrating VLSI Infrastructure to AWS – Challenge Accepted

Zohar Tal
Verification Engineer, Celeno

How to Optimize EDA workload for SAFE-CDP, a Novel Virtual Chip Design Environment on the Cloud

Taeil Kim
Samsung

Ever increasing design size and complex technology requirement in advanced process nodes drive the demand for huge computing power in latest SOC designs to meet tight time-to-market requirement. Cloud now becomes a MUST. To provide shortest path to the cloud for our customers, Samsung Foundry has been working with cloud partners on SAFE(Samsung Advanced Foundry Ecosystem) and come up with SAFE-CDP(SAFE Cloud Design Platform), a virtual chip design environment on the cloud. SAFE-CDP has all things needed for cloud-based design and we went even further by running extensive experiments on the cloud to optimize EDA workload for the cloud. In this presentation, we provide our practice of building up a cloud-friendly environment for Synopsys IC Validator and Finesim by utilizing elastic CPU technology and GPU-based acceleration, respectively.

VC Formal Seamless Scaling on AWS SOCA: A Winning Formula to Shift-Left Verification

Pratik Mahajan
Synopsys

Cloud provides a unique opportunity to get access to hundreds of cores. Moving EDA workloads to the cloud presents a unique set of challenges and considerations. In this presentation we will explore solutions to those challenges by demonstrating how to “seamlessly” scale Formal Verification using Scale-Out Computing on AWS (SOCA). VC Formal on AWS SOCA provides a unique solution to Shift-Left Verification with better performance & convergence.

AMS Simulation Update

Hany Elhak
Sr Dir, Product Mktg, Synopsys

Learn how the latest advancements in circuit simulation can help you reduce the turnaround time of your analog/mixed-signal and memory designs while improving the quality of results.

Panel: Analog Mixed-Signal

Discussion on the latest compute technologies to enable further speedup in simulation turnaround time

GPU-Powered Order-of-Magnitude Speedup for IC Simulation

George Kokai
NVIDIA

Integrated-circuit simulation with SPICE (Simulation Program with Integrated Circuit Emphasis) has benefitted profoundly from multi-core parallel compute technologies in the last decade, achieving a five-to-ten times runtime improvement. As the circuit complexity and size gear up for hundreds of millions of components, however, this approach can no longer address daylong or even weeklong simulation challenges owing to architecture limitations and Amdahl’s law.
In this work, we will present a practical and phenomenal solution that can achieve order-of-magnitude speedup in simulation turnaround time, powered by NVIDIA graphics processing units. In particular, we have developed advanced computational algorithms, techniques, and heterogenous compute management system to make the best possible use of compute resources. This enables massive and efficient parallelism and is able to process within hours trillions of double-precision floating-point arithmetic operations of sparse linear algebraic matrix systems typical of today’s IC simulation.

Game Changer-GPU Simulator for AMS Design

Kihoon Kim
Samsung Foundry

Evaluation of GPU technology on circuit simulation based on Samsung Foundry AMS Design IP.

Flexible and Feature Rich Simulation Cockpit for Netlist

Om Johari
Intel

There are many solutions in the market for schematic based simulation environment, but none for Netlist. Synopsys Cockpit fills this gap and is Flexible and Feature Rich. The tool helps analog and mixed signal design engineer to run simulations in a very interactive way reducing manual errors and its tight integration with waveform and calculator tool makes debug very easy. The Tool also has a rich collection of tcl API’s making it possible to integrate any Internal Tools, Data mine your design and perform other complicated tasks. This presentation will go over the key reasons why we had to pick a Netlist based solution, How we were able to leverage the tcl API’s and automate key tasks to boost productivity of design engineers.

Ensuring Functional Safety of Memory IP Using TestMAX CustomFault™

Kedar Janardan Dhori
STMicroelectronics

Memory real estate is continuously increasing, reaching more than 80% on present day SoCs. In Automotive SoCs, Memory IPs are used for various applications ranging from ADAS to navigation and infotainment. SoCs designed for life critical applications like ADAS (ASIL-D category in ISO26262 standard) go through rigorous functional safety checks and FMEDA (Failure Modes, Effects and Defect Analysis) becomes a necessary step to systematically predict the failure rate of all IPs used in such subsystems. Among various objectives of FMEDA, in this paper, we focus on the requirement for fault analysis and discuss how we are able to use TestMAX CustomFault to perform fault analysis to ensure functional safety of our embedded Memory IPs catering to the Automotive market.

Performing MOS Reliability Analysis with Variability Using Advanced Monte Carlo Solutions

Raed Sabbah
Micron

3DIC Compiler

Panel: A Dash of Science: The Whats, Whys and Hows of a More Efficient Design Process

Achieving PPA goals, reaching timing closure, and meeting project schedules continue to be the Top-3 challenges of the design implementation flow, according to Synopsys users. As designs spiral in both their size and complexity, encompassing ever more functionality into a single system-on-chip (SoC), it grows increasingly challenging to debug, optimize and implement these designs while still efficiently meeting project timelines and the overarching end-product goals. In this session, Synopsys and industry leaders will present new solutions to accelerate design throughput and realize superior QoR while also improving design and project efficiency.

Achieving the Best PPA on Advanced Arm Cores with Synopsys’ Fusion Design Platform™

In this session, Arm and Synopsys experts will highlight the best practices, new methodologies, and enabling technologies that are delivering the industry’s leading power, performance, and area (PPA) for the latest Arm cores.  You will learn about the new capabilities of Synopsys’ Fusion Design Platform being developed and deployed in close collaboration with Arm to enable optimized implementation of these cores to address performance goals for the next generation of smartphones, laptops, hyper-scale cloud computing, 5G, and edge designs. Key technologies that will be discussed include: physically aware RTL restructuring with RTL Architect, signoff-driven ECO closure with PrimeECO, in-design power integrity analysis and fixing with RedHawk Analysis Fusion, H-Trees with MSCTS, hierarchical design and, placement attractions methodologies.

End to End Low Power Solution User Challenges

End to End Low Power Synopsys Solutions

Godwin Maben
Synopsys

*User Presentation

Billion Gates Power Analysis Using Emulation

Alexander Wakefield
Synopsys

This presentation will explain why looking at power analysis holistically using workloads running on the full SoC opens new opportunities for design teams to increase competitiveness of their products and reduce project risk. We will introduce breakthrough emulation technology that enable multiple analysis iterations per day.

Low Power Verification

VC PSS Tutorial

Bernie DeLay
Synopsys

PSS is used to capture functional intent, which can then be used regardless of the verification stage. The functional intent is represented as a stimulus model written in the PSS language. This tutorial will show how Synposys solution enables porting stimulus to many different environments from single source; Generation of many intelligent test cases from a succinct model and creation of coverage-driven, system-level test cases targeting bugs, which are difficult to detect, at the System Level

Integrated Development Environment (IDE) with SystemVerilog On-the-Fly Checks

Eldon Nelson
Verification Application Engineer, Synopsys

Introducing Euclide - IDE with On-the-fly Design and Testbench checks highlighting intergration with Verdi, VCS and ZeBu for improved productivity, performance and compatibility

*A Robust Flow for Recreating Obsolete Components using FPGAs

Driving Efficiency & Productivity in SoC Verification Sign-off with Unified Verification Management Automation

Kirankumar Karanam
Synopsys

This presentation is on improving verification productivity by unifying and automating Verification Continuum flows. We will show the latest advancements and results from the natively integrated VC Execution Manager solution.

Higher Coverage, Half the TAT with VCS -- Driving Verification Efficiency with AI/ML Innovation

Will Chen
Synopsys

See how VCS's new Intelligent Coverage Optimization and Dynamic Performance Optimization Technologies deliver unique ability to improve verification efficiency and productivity

Driving Physical Signoff Convergence at Advanced Technology Nodes

Captain Liu
TSMC, Synopsys

Increasing design and manufacturing complexities at advanced nodes (7nm, 5nm and below) pose significant challenge for physical verification engineers to achieve on-time design closure. IC Validator continues to innovate in scalable performance, high productivity and robust debugging.  In this presentation, TSMC talks about partnership with Synopsys IC Validator on technology collaboration and tool enablement for TSMC’s advanced process nodes. Synopsys provides an overview of latest IC Validator innovations for physical verification productivity and how to deploy these technologies to achieve faster physical verification closure.

Shift-Left LVS Closure: IC Validator Explorer LVS

Jinsik Yun
Staff Corporate Application Engineer for IC Validator, Synopsys

IC Validator Explorer LVS provides a fast and automated way to find root causes of the early full-chip LVS issues. By swiftly detecting design issues, Explorer LVS delivers results up to 30x faster than a traditional LVS flow, enabling more frequent and shorter iterations of running/debugging/fixing design issues and eventually faster LVS sign-off closure.

IC Validator Based Physical Verification Methodology for High Full Flow Productivity

Namit Varma
Achronix

With increasing DRC complexity at 7nm and large design sizes, physical verification turnaround time has become a key challenge to deliver tape-outs on schedule. In this presentation, Achnonix discusses physical verification methodology with IC Validator and how this methodology was successfully deployed on latest designs to enhance full flow productivity and accelerate design closure.

*Full Chip Antenna DRC Runtime Challenges and Solutions

Sie Ang Wong
Structure Design Engineer, Intel

*Secure Cloud-Based Lynx Virtual Design Environment Enabling Accurate and Efficient Physical Verification and Fabrication Signoff

Lifu Chang
Director, The MOSIS Service

High Performance Layout Analysis with IC Validator Workbench

Peter Thwaite
Synopsys

IC Validator Workbench is a must-have utility for IC Validator physical verification flow. It enables efficient viewing and editing of Layout databases:  Quickly open layout database and access the graphical data for fast review and editing, Compare Layout databases, Automate repetitive tasks using standard scripting languages (Tcl or Python).  IC Validator Workbench can also be used to efficiently merge multiple database files into your complete design for chip finishing. Additionally, the full array of IC Validator tools are integrated and accessible in IC Validator Workbench environment to make design verification easy to accomplish.

*User Presentation

*Low Power Verification and Emulation of Automotive SoC

Billion Gates Power Analysis using Emulation

Alexander Wakefield
Synopsys

We will explain why looking at power analysis holistically using workloads running on the full SoC opens new opportunities for design teams increase competitiveness of their products and reduce project risk. We will introduce breakthrough emulation technology that enable multiple analysis iterations per day.

SAM based full chip Multi-Voltage Verification in VC LP

Balaji Vishwanath Krishnamurthy
Intel

Instance count in the netlist of full chip Graphics IP has increased exponentially in recent programs, posing roadblocks in Multi-Voltage (MV) Verification Signoff.  At the same time, tighter schedules have required design teams to reduce iterations and time available for verifying the design.  A full-blown chip level netlist either does not load into the VC LP tool or offers unreasonable verification run times. Black-boxing ‘placed and routed’ blocks in the netlist leads to critical verification coverage losses, creating a need for scripted checks thereby resulting in a delayed and low-confidence MV sign-off. This article discusses a Static Abstract Modelling (SAM) based chip level MV Verification using VC LP, that successfully enables handling the large size of the design (no tool capacity issues), without compromising MV sign off quality. The feature is based on retaining only the necessary logic gates and connectivity, required for verification, within the chip level netlist. Using SAM in VC LP, we were able to demonstrate at least a 3 week faster and highly reliable MV sign off. In our tests, SAM based VC LP simultaneously achieves increased verification coverage by up to 9% w.r.t our baseline runs, eliminates the need for any external MV checks and improves debug-efficiency by at least 25%. SAM based methodology is now and will be the new norm in MV verification especially for growing designs.

*Pre-Silicon Functional and Power Validation using Gate-Level Emulation

KEYNOTE - Zero Trust Microelectronics: A Model for Hardware Security Evolution

Dr. Brian Dupaix
Data Driven Quantifiable Assurance Project Area Lead, AFRL

Application of Zero Trust principles across the microelectronics lifecycle has the potential to raise confidence in the components available for implementation in safety-critical systems that have an ever-increasing role in society. However, since Dr. Lisa Porter (DUSD(R&E)) advocated for a new “Zero Trust” paradigm for securing microelectronics at DARPA ERI in 2019, the hardware community has raised concerns regarding the meaning and application of Zero Trust principles for hardware. This presentation returns to the first principles and foundational tenets of Zero Trust established by the cybersecurity community and provides an initial mapping for their application to stages of the hardware lifecycle with the objective of outlining how application of security controls at the appropriate points can uplift the confidence in implemented microelectronics.

Lessons Learned in Designing and Verifying Secure System-on-Chip

Jean-Philippe Martin
Security Lead, Intel

This talk will address where common vulnerabilities are introduced during the design of an SoC, how good practice can help security assurance when designing logic, integrating IPs or performing pre-silicon verification.

A Robust Flow for Recreating Obsolete Components Using FPGAs

Francis Bruno
FPGA Engineer, ASIC Solutions

Some custom VLSI technology is approaching 40 years of age. End of life buys and obsolete technology or destroyed mask sets may make buying new parts impossible. Luckily, FPGA technology has become more affordable, faster and large enough to reproduce most VLSI designs or even boards from 20+ years ago. In this paper I’ll introduce a flow for re-implementing a legacy design in an FPGA.

A Framework for Assessing the Vulnerability of ICs Against Fault Injection Attacks

Huanyu Wang
Research Assistant, University of Florida

Fault-injection attacks have become a major concern for hardware designs, primarily due to their powerful capability in tampering with critical locations in a device to cause violation of its integrity, confidentiality, and availability. Researchers have proposed a number of physical and architectural countermeasures against fault-injection attacks; however, these techniques usually come with large overhead and design efforts making them difficult to use in practice. In addition, the current electronic design automation (EDA) tools are not fully equipped to support vulnerability assessment against fault-injection attacks at the design-time to avoid tedious manual design review. In this paper, we propose an automated framework for fault-injection vulnerability assessment of designs at gate-level using Synopsys Z01X, while considering the design-specific security properties using novel models and metrics. Our experimental results on the security properties of AES, RSA, and SHA implementations show that the security threat from fault-injection attacks can be significantly mitigated by protecting the identified critical locations, which are less than 0.6% of the design.

DoD State-of-the-Art Enterprise Hardware Emulation

Dr. Christopher Diltz
Edaptive

The microelectronics landscape is rapidly changing for the DoD, as integrated circuit and system design complexities and hardware assurance requirements increase owing to high-performance mission critical requirements and the need to protect sensitive data. The DoD data center has unique requirements uncommon to the commercial world. Corporate suppliers deal primarily with relatively static projects for hardware emulation configuration before switching to a new project and new data center configuration. The low project/configuration change velocity is a benefit for corporate solutions that the DoD heterogeneous user/project base cannot leverage. The successful DoD data center must address the more complicated challenges associated with a very high change velocity. This atypical aggressive use model delivers the DoD significant economic advantages, though at the expense of up-front implementation cost. For current and future DoD requirements, this paper outlines decisions and processes that will provide the DoD with improved performance and higher reliability at lower cost than current best practices allow. Keywords—Trust, Enterprise, Data center, Simulation Acceleration, Hardware Emulation, Verification, Hardware Assurance

Challenges and Approaches to Secure Hardware Design

Dale Donchin
Senior Program Manager, Synopsys

Security hardening during the design creation flow has traditionally been very challenging. Every design group seems to have a unique flow, and every application has differing security requirements. These factors often drive increases in the power and area and decreases in the performance of the integrated circuit. There are multiple threats and many types of defenses already existing and new threats coming daily. How can developers expose and mitigate vulnerabilities during design creation while still considering competing design requirements? What steps are necessary early in the design flow to ensure proper chip provenance, authentication, provisioning, test, debug, and threat detection post tape-out? This tutorial presents how Synopsys, under a DARPA-sponsored program, is addressing these challenges.

*Min-Max Contention Aware Clock Planning in Mega Hierarchical Designs

Wan Chong Khor
Technical Lead, Intel

*User Presentation

*50% Reduction in TAT Using Signoff-driven ECO Closure

Cheoljun Bae
Samsung

ECO closure is a major bottleneck for design closure and can result in tapeout delays due to the unpredictable nature of late stage ECO changes during the signoff stage of the design. In this presentation we will share a methodology and practical results of how we reduced of our ECO closure cycle by 50% by deploying Synopsys’ signoff-driven ECO closure solution

*User Presentation

Estimating DVD-Induced Timing Impact Using PrimeTime® and Redhawk-SC

Jongyoon Jung
Staff Engineer, Samsung

In this work, PrimeTime's new DVD analysis has been proved. The new method of PrimeTime is able to directly read Redhawk-SC's DVD report and estimate its impact on timing. It is shown that the new method is well correlated with quad-core ARM CA53 chip implemented in Samsung's LN10LPP process.

PrimeTime® Technologies for Designers’ Productivity

Arundas Haridas
Manager I, Synopsys

Dramatic rise in design size and complexity has lead to a slew of signoff challenges that affect designers’ ability to meet TAT target. In this tutorial, major advances in PrimeTime to address these challenges will be reviewed. We will cover new techniques to improve productivity, such as reducing report runtime bottlenecks, managing number of corners in multivoltage design, and reducing runtime & memory requirement for hierarchical designs.

Cost-Effective Characterization on Arm based AWS Graviton2 Processors Using SiliconSmart®

Ajay Chopra
Director, Arm

Characterization is a compute intensive exercise and the demands are growing by the day to capture more views in more accurate forms. Moments LVF, high-sigma accurate requirements, EM are a few examples of more views emerging in more accurate forms, pushing the demand for compute through the roof, when factoring shrinking time-to-market requirements. While everyone’s working hard to innovate to address these challenges, we at Arm, in collaboration with Synopsys, present our contribution to this game my marrying two concepts – Cloud Computing and Arm-Core Execution. Cloud computing offers amazing scalability with the right mix of software and configuration, thereby helping us meet the compute demands emanating from our time-to-market requirements. However, there is a cost associated and this must be profitable over the incumbent on-premises approach, to turn heads.
This is where Arm based AWS Graviton2 processors comes into picture, they are not only fast but also cost effective hence execution on Arm-powered cores, instead of the conventional x86-powered cores, is the magic wand that helps us achieve our objectives. This paper talks about how we power our characterizations using SiliconSmart on AWS using Arm Neoverse based Graviton2 instances.

Massive Scalability to 120k Cores for Library Characterization

Library Characterization has typically been a long pole in a design cycle. With ever more demand for accuracy at lower technology nodes, liberty formats has evolved, and the more intricate amount of data help static timing/power analysis and place and route tools to reduce signoff pessimisms. This comes with a cost of simulating more data. To deliver this in a timely manner, highly distributed, massive computing resources are required. Massive scaling of distributed computing resources requires the balance between the handling of the hardware, the handshake between the resource management system and the application being executed. Using parallel distribution technique, systematic partition of the data systems and license check out scheme, we were able to scale our library characterization from a typical compute farm of 30k CPUs to 120k CPUs, allowing us to quadruple the throughput where necessary when additional characterizations are needed on an on demanded basis.

Unified Library Characterization and Validation Solution Targeting Advanced Nodes

Fazela Vohra
Sr. Manager Applications Engineering, Synopsys

High Performance, High Accuracy, High Reliability are the corner stones of lower technology node characterizations and libraries are the solid base of any successful chip tapeout. With our new Next generation Characterization Product – we aim to achieve all of these goals and then some more. Next Generation Product is fully backward compatible with SiliconSmart ADV thus offering a seamless path to upgrade and also embeds the support for Next Generation simulator product. This tutorial will take you through the introduction of Next Generation of characterization product, all its current new offerings and an exciting roadmap of the upcoming features.

TestMAX Manager for RTL-Based Test Flow

Tammy Fernandes
Synopsys

Under pressure to meet design schedules, design-for-test (DFT) engineers and teams must quickly architect, implement and validate increasing complex DFT logic. The complexity continues to rise as the challenge to meet manufacturing test quality and cost goals for many newer-generation designs are met by using sophisticated test techniques. This session will provide an overview and relevant details of Synopsys TestMAX Manager and new flow guidance to enable easy implementation of major RTL DFT components such as compression logic, logic BIST, memory BIST, and access networks. In addition, connections to DFT functionality validation will be covered as well as connections to synthesis-based test for lower-level, essential DFT (example: scan chains), accelerating the entire DFT effort.

TestMAX Manager Flow for Scan Static Timing Analysis (STA) Optimization

Badiger Pavan, Lamin Shen
Intel, Synopsys

TestMAX Manager flow was used in an Intel SoC project for design-for-test (DFT) implementation, providing a highly automated process to insert scan IP at the RTL level as well as generating design constraints that were passed to synthesis and physical design integration. This Intel SoC design was one of the pilot projects that adopt a complete TestMAX Manager flow from RTL to GDS. This project demonstrates a large scale design with a complex design structure. Though TestMAX Manager flow provides an integrated scan IP insertion, scan synthesis and timing constraints, there are significant design specific modifications needed to overcome the challenges caused by complicated clock tree design. This presentation provides an in-depth analysis of the on-chip clock (OCC) controller and clock structure. It also gives a practical static timing analysis (STA) scan constraint guideline that can be referenced in other similar designs.

*A Hybrid ATPG and Logic BIST Architecture for Extreme Compression

Jon Colburn
NVIDIA

Design-for-test solutions need increased capabilities as device complexity increases and semiconductor integration changes. Large complex devices at advanced process nodes require more rigorous testing methods and more test content. Test compression provides a method to deliver more test content through a limited number of tester channels. Using a hybrid system that supports deterministic test pattern generation and pseudorandom pattern application it is possible to make better tradeoffs between coverage, test data, and test time. The combination of TestMAX DFT and TestMAX XLBIST comprises the hybrid solution that scales to support testing over a range of different access methods from low pin count test access port (JTAG) to wide input/output connections. It reduces test time by supporting the delivery of fast external data and match internal scan speed to higher I/O speed.

*User Presentation

New Pattern Conversion Technology

Pallav Gupta
Intel

Intel is working to replace an internally developed CPU-centric pattern conversion methodology with a more streamlined approach with a widely adopted third-party tool while still meeting the needs of different business segments. Intel partnered with an EDA vendor to drive enhancements to the pattern conversion methodology as well as is managing total cost of ownership. This allowed for standardization and simplified conversion of STIL patterns. The new pattern conversion methodology with specific customization maintained the requirement for high volume manufacturing within Intel’s ecosystem.

Addressing Hierarchical and Burn-in Test Requirements with a Test Fabric

Marco Casara
STMicroelectronics

Design complexity and size continue to grow, requiring the need for hierarchical test by partitioning designs into smaller parts to make design-for-test (DFT) and ATPG manageable as well as decreasing test bandwidth needs.
Burn-in test is also a requirement for detecting early failures by testing the product to operate in extreme temperature conditions for a time longer than manufacturing test. High parallelization to minimize test cost is usually required in burn-in, with fewer channels available than manufacturing test.
ST Microelectronics’ requirement for hierarchical test and burn-in are met with the introduction of a test fabric, a new Synopsys technology.
The test fabric helped to meet hierarchical test requirements, by supporting pattern porting in two different modes, parallel for manufacturing test, and serial for burn-in test. ATPG patterns generated at partition level can be ported to the top and can be re-used for both manufacturing and burn-in test.
In this presentation, the application of the test fabric is covered, experimental data from DFT and ATPG are also shared.

*User Presentation

*Metastability Bugs Prevention via CDC and RDC Verification: Learnings from SoC Design

*Noise Reduction using Static and Formal Aware Linting in a Single Phase

*Scalable RDC Signoff Methodology for Large SoCs

*Efficiently Solving the Challenges of Clock and Reset Domain Crossing Verification for Large SoCs

*Lint Abstract Flow – A Hierarchical Approach to Enhance RTL-checking Quality with Faster Turn-around

*User Presentation

*KIAS (Known Issues And Solutions) - A Way to Capture Solutions of Already Debugged Issues and Present as Information to Users Whenever Error is Logged Again

*User Presentation

*User Presentation

*Delta-cycle Glitch Caught by Specific GUI Tool Selection

*User Presentation