For decades our industry has focused on achieving improvements to semiconductor speed and area – and we have accomplished that. But looking at advancements in semiconductor technology leads naturally to an examination of what those advancements can deliver. Chips are poised to massively change our world. The superior performance of today’s semiconductors, multiplied by the capabilities of artificial intelligence, enable us to collect and analyze data such that we can now anticipate potential problems, in domains such as human health and climate. And the same technology enables application of AI to model and optimize solutions to improve human existence. Synopsys Founder and co-CEO Aart de Geus kicks off SNUG with a look at how decades of semiconductor advancement enable unleashing the potential of semiconductors, computing, data analysis and AI in ways that hold the potential of transforming human existence.

Daniela Rus of MIT sees Artificial Intelligence as a technology with the broadest potential for business and societal impact, even as she acknowledges that impact isn’t quite clear. Asked to assess which outcome is most likely – a forecast that AI will contribute to enhanced productivity and job creation, or the possibility it will create better lives, or concerns it will foment unemployment – Dr. Rus answers, “Probably all of them.” She has said “If we make the right choices and the right investments, we can ensure that those benefits get distributed widely across our workforce and our planet.” Join us as Dr. Rus speaks on AI from the perspective of its impact on us and future generations.

High Performance Computing (HPC) is one of the fastest growing design segments in the semiconductor industry, powering a wide span of applications including cloud data centers, artificial intelligence, mobile computing, autonomous vehicles, and many more. In this panel, speakers from various areas of HPC applications will discuss the challenges in HPC implementation and signoff, as well as the unique Synopsys solutions deployed to ensure robust PPA and fastest time-to-market.

A robust discussion on cloud trends and the future of cloud for EDA. We’ve all been hearing about cloud and how it’s the future for EDA workloads. We’ll be talking with key industry players to dissect and understand how this future is here now, what cloud means for EDA, and how you can use the cloud to address the demand for ever-increasing compute resources in a tight supply chain environment with no end in sight.

Aart de Geus has laid out a vision of improving overall design productivity by 1000X this decade. Achieving this vision will require fresh ways of thinking about analog design, which largely remains mired in the same manual, time-consuming methodology that has been used for decades. In this panel, experts from several leading semiconductor companies will talk about analog design productivity challenges and share some real-world experiences from adopting modern solutions.

Women have made enormous strides in the engineering workforce in recent decades, but much more opportunity lies ahead. What have been the positive outcomes that a growing percentage of women engineers brings to design and development? What pinch points linger? What potential lies ahead? Join us for an insightful 45-minute panel with four key women in engineering who will describe the challenges and opportunities they’ve experienced in their careers, their inspirations and their hopes for a more inclusive future.

Hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project, as well as discussions about the latest developments in the verification landscape with a software-first approach and intelligent verification technology.

As 3DICs make their way into the mainstream, they bring potential to shape a new scaled-up, data-driven and processing-centric economy. By providing unfettered performance scaling in physically constrained footprints or allowing a heterogeneous mix-and-match approach to maximizing target-application-optimized process technologies, 3DIC technology offers vast potential.

In “A Conversation with Sassine Ghazi,” SNUG Technical Committee Chair Savita Banerjee speaks with Sassine Ghazi in his first time at SNUG as president at Synopsys. Sassine and Savita are expected to cover a wide range of topics, such as trends he sees in the industry, how Synopsys keeps its innovation edge and what have been some of the exciting times he has seen at Synopsys.

Designers have realized that for some high-performance computing (HPC) and networking applications, monolithic SoCs are no longer an option. Die-splitting and disaggregation are driving the shift to multi-die integration with new requirements that designers must consider for maximizing SoC scalability and yield. New use cases, such as co-packed optics, are relying on efficient die-to-die connectivity to benefit from this industry trend. The industry is developing new 2.5D or 3D packaging options and standards for 112G/56G USR/XSR SerDes and OpenHBI, AIB parallel links that help make tradeoffs between density, power and complexity. This presentation demystifies the world of 3DIC design by explaining the drivers for multi-die SoC architectures and highlights the characteristics of a reliable die-to-die interface with lowest latency and power consumption.

Semiconductor industry is migrating towards disaggregated designs for better power, performance and area (PPA), where two or more dies are stacked vertically with a dense array of microbumps (uB) and interfaces connecting to the C4 bumps. The most challenging aspect of 3DIC design  is package side C4s, base die microbumps and top die microbumps plan. The distribution of C4s and microbumps are tightly coupled and a 3DIC tool enables visualize the three bumps hierarchies providing opportunity to better optimization and TAT.

This presentation will discuss how to co-design C4s and microbumps. It describes the setup using Synopsys’ 3DIC Compiler platform to efficiently build, validate and analyze the 3DIC bump plan. For optimizing power delivery and reduce bump plan complexity, 3DIC tools are used for providing critical feedback to floorplan. The utility of 3DIC tool is extended to automate die-to-die, general purpose IOs and other IPs like PCIE, DDR signal bump placement. The 3DIC implementation tools brings top and base die in same framework for co-planning C4s and microbumps which is a function of top and base die process, voltage rails, signals and test(SORT) requirements.

With new bonding technology innovations, customers are integrating multiple dies in 3DIC stacks to realize high-performance silicon and reduce the chip costs by mixing multiple technology designs in a single product. Multi-die stack integration leads to profound challenges as each individual die can vary in process technology, have varying number of corners, and have different orientation and modes. The cumulative increase in parasitic capacitance associated with multi-die stack is the dominating factor limiting the operational speed of the product. Smart technologies using 3D-field solver-based accuracy in extraction, and advanced simultaneous multi-corner in timing analysis and ECO are needed to accurately tapeout the design.

In this presentation, we will present the Synopsys Signoff flow using StarRC, PrimeTime, and Tweaker ECO to effectively and efficiently signoff and converge multi-die 3DIC designs to achieve the best design closure.

Historically, design teams and package teams had been separated by a wall above which they throw the infamous excel bump maps to communicate bump locations, changes in the design, etc. In order to tear down this wall, we enabled 3DIC Compiler as a common playground for design and package teams. Having a common environment where both teams can work on the same database reduces number of iterations and minimizes errors due to database transfers. The design team benefits from the rapid prototyping capabilities of 3DIC Compiler, and being able to see package information in a tool environment very close to the one for ICC2 or Fusion Compiler. Meanwhile, the package team can explore the ASIC design in a layout GUI, highlight changes from previous versions, generate design collaterals for other tools and even implement design changes if needed. On top of this, a common database solves version control and data consistency issues for both teams. In this presentation we will showcase how we use 3DIC Compiler to achieve some of these benefits, as well as our plan to achieve the rest in the near future.

With the semiconductor industry’s growing adoption of multi-die 3DIC and chiplet based systems, new embedded test & repair solutions are essential throughout the lifecycles of individual dies, interconnects between the dies, and the assembled multi-die packages. These systems also require new high-speed, high-bandwidth, communications interfaces, such as HBI, XSR, and HBM between the dies and/or chiplets.  Such interfaces enable multi-die stacking, assembly and packaging using various stacking architectures, such as 2.5D and 3D, for logic-to-logic and logic-to-memory die interfaces. This tutorial provides a brief review of the embedded test and repair requirements for 3DIC and chiplet based systems and describes Synopsys hierarchal solution, which manages test, calibration, repair, and debug, of the inter-die silicon and intra-die interfaces. This solution also leverages multiple synergistic IEEE test standards, including 1149.1, 1838, 1500 and 1687. 

In the two years since introduction, Synopsys’ DSO.ai™ has enjoyed rapid adoption around the globe and across varying market segments. With growing usage on real-world designs, customers have applied the power of DSO.ai and its learning system to optimize varying aspects of the chip design workflow. In this session, Synopsys experts will showcase the library of design-space applications (aka “SpaceWare apps” ) deployed by customers, highlighting those that are readily available to jump-start key design tasks and unique apps that have been built using the customizable environment in DSO.ai.

In the world of semiconductors, we have undoubtedly entered the era of Artificial Intelligence (AI) everywhere. AI-driven solutions like DSO.ai are already delivering unprecedented productivity and PPA benefits and we can certainly expect its impact on chip design will only continue to grow. But where are we headed on this AI journey? Join us for this visionary fireside chat session with MediaTek as they share their experiences with applying DSO.ai and discuss future opportunities for the road ahead.

For today’s semiconductor industry, large SoCs with enabling multiple functionality is a common trend. With multi-million instance count designs, achieving faster turn-around-time with optimized PPA is very essential to product’s cost and survivability. Using data for self-learning machine learning, is one such Novus capability that EDA vendors are providing in their design tools. Using such DSO.ai tool capabilities to achieve best possible PPA for a given design, and using it to make optimal selection of std.cell library for faster RTL2GDS design cycle is demonstrated in few of FPGA based design that Intel uses in PSG team. In this paper, we list out challenges around complexity of design, runtimes related to large scale design and how various PPA metrics are measured and results used for production ready design. DSO.ai is used for design with internal intel processes as well as external process and we have results tabulated on both such testcases.

In mobile CPUs, one of the most important design goals is to improve benchmark score and battery time. Benchmark score is a measure of how quickly a workload finishes within a given power/thermal budget and battery time determines how long a CPU can keep running. The power consumption (P) vs operating frequency (F) curve of a design is the key factor that determines the benchmark scores and battery times. By changing the shape of the curve, benchmark scores and battery times can be improved (or degraded)The shape of the P vs F curve can be changed by optimizing a design at different voltage Vopt and a different target frequency Ftarget. However, there could be too many combinations of Vopt and Ftarget because most CPUs need to be optimized at multiple PVT corners. Exploring the combinations of Vopt and Ftarget to find out the best one requires a lot of time and computing resource. The goal of this presentation is to share an AI-based method developed using Synopsys' DSO.ai learning system to optimize for best Vopt and Ftarget combinations that maximize benchmark scores and battery times of a given design.

Nowadays, due to the high functionality and complexity of optimization tools, the number of options and commands has increased, and when combined with design methods and process technologies, there are innumerable combinations that designers must be aware of. Under such circumstances, Sony is working to maximize design added value by improving PPA by developing its own method for developing CMOS image sensor products. However, increasing the time and man-hours required to search for an option that meets the optimum target has become a major issue, and it is essential to establish a method for quickly deriving the optimum option. This time, we have confirmed that better results can be obtained with less man-hours by applying DSO.ai, which efficiently searches for the optimum design flow and setting options using AI / ML. In addition to introducing such cases, we will also introduce future efforts to further maximize the value of PPA.

The latest ICO (Intelligent Coverage Optimization) technology developed by Synopsys in VCS leverages Machine Learning (ML) to cover the randomization space faster. This leads to accelerated coverage closure. In this session we will present our findings on using ICO with two use-cases. In the first case, ICO was used on a stable regression where we explored it to achieve 100% coverage faster. In the second case, the testbench was in development and the goal was to see if we can find corner-case bugs earlier and expose testbench issues.

To face increasing demand in SoC for Functional Safety and Security, ST is developing custom processors implementing mechanisms that satisfy ISO26262 safety requirements and protect program execution against physical attacks.

Fault injection is well known methodology for semiconductor IP to support the evaluation of the hardware architectural metrics and the diagnostic coverage of safety mechanisms. However it takes a large amount of effort and time as the IP scales up. This session will introduce our effort in workload selection, fault sampling and simulation results analysis for reducing fault injection runtime.

The MIPI Alliance has been developing and deploying camera and display protocols for the automotive semiconductor industry for years. Their vast success in the mobile industry is now leveraged in applications such as automotive ADAS and infotainment. This session will briefly outline the latest automotive MIPI camera and display protocols and how they are helping designers simplify integration of cameras in the car, improve interface for high resolution, and support safety and security. In addition, Valens Semiconductor will use their long reach automotive design for in-vehicle connectivity to describe how they used Synopsys

As automotive systems become ever more complex, their development requires a consideration of all aspects required to create a dependable product: the system function, its performance, its reliability, its power consumption, and of course – its safety from unreasonable risk to its users, and its ability to protect from security threats to the user or to the manufacturer.

For minimizing hazardous events and maximizing threat protection, established engineering disciplines of Reliability, Behavioral Safety, Functional Safety, and Security must be applied in an appropriate sequence and sometimes with sophisticated intertwining and arbitration of their measures.

This SNUG 2022 lesson presents a new development life cycle as developed in frame of IEEE P2851 standard and shows the needs for SoC design and verification from Requirements Elicitation to Tape-out. It closes with the presentation of offered solutions in the frame of SYNOPSYS EDA Tool landscape.

Significant progress has been made to improve safety of the underlying hardware in Automotive designs through deployment of ISO26262 methodology. However, security weakness in the SoC hardware and the software running on those hardware can lead to vulnerabilities that may be exploited later by malicious hackers and bypass safety measures. Hence comprehensive security solutions required which span software to hardware to prevent security attacks on the following attack surfaces – detection of trojan implant to trigger malicious behavior during operation, supply chain integrity to ensure trust-worthy components are in use, side channel attack prevention to ensure integrity and fidelity of the system and prevention of reverse engineering to re-create security-critical hardware by malicious actors.

These challenging problems need to be addressed throughout the design flow – from early RTL design, to pre-silicon system-level validation of hardware with software stack to software validation for security bugs. Synopsys security vision encompasses secure design and verification across software and hardware used in security-critical systems. This presentation will discuss recommended methodology and best practices to address common weakness enumerations (CWE) and add counter measures to build threat and fault resilient designs. 

With functional safety in EE systems becoming increasingly prevalent, it is important that the work products as required by ISO-26262-2018 are prepared with evidence from the verification and validation (V&V) activities. This paper describes how qualitative and quantitative evidence can be analyzed to close the loop to requirements. The presentation describes the V&V activities of the safety related activities in a safety element out of context (SEooC) IP, approaches on how it is used in a sub-system and system at higher tiers. Special emphasis is added to the development of work products related to quality management and functional safety as verification activities and how the safety analyses work products intend to verify the Technical Safety Concept. The presentation also describes the roles of tools and methodologies in the V&V safety related activities and illustrates with an example.

The Failure modes of each component in the design and the distribution of component failure mode on the product functionality are measured by the Failure Mode Distribution (FMD) of those failures. The FMD is entered as an estimation value in FMEDA is deemed acceptable for ASIL A/B. But, ISO26262 requires a quantified analysis of FMD for traceability especally for ASIL D. There are several approaches in presenting the FMD data, based on a qualitative pin distribution analysis up to quantitative analysis. This presentation shows an automated tool-based flow and introduces the quantitative FMD calculation and reportng through TestMAX FuSa tool. An example will be presented by Synopsys Solution Group detailing how TestMAX FuSa is used in the functional safety development flow and the quality of the reported results compared to other approaches. FMD is an important input to the FMEDA of ARC Processor cores. Usage of an advanced methodology through quantitative analysis gives higher accuracy in results during the safety analysis. This also allows to arrive at a more precise estimation of SPFM metric for a combination of different safety mechanisms including software-based self-test running in ARC processor core.

The rapidly increasing complexity of electronic functions in automobiles comes through the increased processing power of integrated circuits and the complexity of software running on those. In the post-Moore era, processing power is enabled by heterogeneous processing units. This trend requires application domain experts to become not only safety experts but also experts in programming specialized processors. This negatively affects the cost and time to market for new features. Model based development (MBD) appeared as a solution to meet the highest levels of safety requirements with less effort. Today, MBD also becomes a turnkey approach for cost efficient utilization of special purpose programmable hardware accelerators. This presentation covers the theory introduction as well as the practical aspects of model based development for ARC Processor IP implemented in Infineon Aurix TC4x solutions.

Automotive SoC designs are becoming more complex and must meet stringent ASIL D functional safety (FuSa) requirements for applications such as ADAS and autonomous driving. These requirements must be captured in a management system (RMS) and fully addressed at every phase of the SoC design lifecycle. Safety mechanisms are identified during safety architecture exploration and high-level safety analysis and must be implemented and verified. Typically, these activities demand significant time and resources and are driven by error-prone manual processes that are not optimized for FuSa. In this session, Synopsys introduces safety specification format (SSF) to automate FuSa aspects of the end-to-end SoC design lifecycle. The SSF describes a common safety intent such as hardware safety mechanisms deployed in automotive IP and throughout the design. The safety intent described in SSF ensures a consistent user interface across Synopsys

Even though the automotive industry has been around for more than ten years, it continues its tremendous rise and revolution in the semiconductor industry. The transformation has affected all the segments and, in particular, the built-in self-test (BIST) and self-repair (BISR) on-chip infrastructure. The requirement is not only to obtain high fault coverage, but also to ensure functional safety compliance. Today, there is a trend towards more automotive applications that require increased data bandwidth and external storage. This is where external memories including DDR and HBM families come into play, and conventional test and repair IPs should be appropriately adapted for testing external memories. In this presentation, an efficient on-chip built-in self-test and repair (BISTR) solution is proposed for comprehensively testing and repairing the external memories throughout the entire lifecycle.

Functional safety has become a critical requirement for Automotive SoCs with increasing levels of autonomy for vehicles, with the ultimate goal of truly driverless automobiles. A key ingredient of ensuring safety in the automobile is In-System BIST which has to be invoked during power-on/power-off cycles and periodically during mission mode operation. We present the unique challenges posed by In-System BIST across In-System BIST architecture, implementation and software. In-system BIST has to comprehend the unique constraints imposed by test execution in a functional system such as isolating rest of the functional logic from random transitions created by partition under BIST, keeping BIST power staying under the system power budget so as not to cause failures during mission, executing BIST to obtain the desired coverage within the allowable boot latency and ensuring secure execution in the field free from malicious attacks. In addition, In-System is not expected to have unreasonable impact on Power-Performance-Area (PPA) of today

Fault simulation is a key component used to measure metrics for the effectiveness of safety mechanisms for FMEDA.  Synopsys will introduce in this session the latest state of the art solution for digital fault simulation.  VC Z01X is a new concurrent fault simulator using the VCS simulation engine.  The presentation will discuss the motivation for introducing a new solution, advantages of the product, and some of the new use models and capabilities enabled with VC Z01X.

Wireless communication is at the heart of the technological revolution of the past few decades and RF circuits are what enable wireless systems to communicate with each other. The design and characterization of RF circuits is a complex process that requires the designer to account for a variety of challenges. In addition to the challenges posed by modern semiconductor processes and the growth of modern standards such as 5G, the designer must also account for electromagnetic effects that become significant at RF and mmWave frequencies. The Synopsys Custom Design Platform provides a holistic way of solving the RF Designer’s challenges, from the integration of industry-leading tools for accurate EM modeling of critical components, the simulation and post-processing of important RF measurements, to layout creation and accounting for physical effects.

The methodology is used to provide high performance register file IPs for internal customers. Automation is key to produce a large library of RF IPs with sufficient breadth. A parameterized model, written in Tcl, is configured to generate a library of register files effortlessly and quickly. The Custom Compiler RPL package provides foundational capabilities for the parameterized model.

Today’s hyper-convergent systems consist of larger and faster embedded memories, analog front-end devices and complex I/O circuits that communicate at 100Gb+ data rates. The design complexity increases further as stacks of DRAM chips connect to the SoC in a system-in-package design. These circuits are designed at advanced process nodes suffering from higher parasitics, lower noise margins and increased variability. Verification and signoff of these circuits requires more simulations with longer runtimes at higher accuracy requirement, impacting the overall time-to-results (TTR), quality-of-results (QoR) and cost-of-results (CoR).

The Synopsys PrimeSim Continuum circuit simulation solution uses NVIDIA A100 GPUs to improve time-to-results by 5-10X compared to simulations running on CPU alone. The solution consists of advanced computational algorithms, techniques, and a heterogenous compute management system to make the best possible use of compute resources. This enables massive and efficient parallelism and can process within hours trillions of double precision floating-point arithmetic operations of sparse matrix systems typical of today’s IC simulation.

This work will explain how A100 Tensor Core GPU can accelerate time-to-results for circuit simulation without any approximation that would impact the quality-of-results. Simulations of state-of-the-art IC designs are provided to compare run times and accuracy using A100 GPU, V100 GPU and CPU only.

Engineers have been deploying Custom Compiler's visually-assisted layout automation technologies to achieve reduced analog layout TAT and improved QoR. Our features have also been evolving to provide more productivity and ease-of-use. In this session, we will be showing the favorite features highlighted by experienced layout designers all over the world. We will cover analog and custom digital placement and routing for both device-level and block-level to achieve high quality custom layouts.

One of the biggest challenges in signoff flow is that after post-layout simulation using completed layout DB, if simulation results differ from the intended values, a lot of time is needed to correct it. As one of solutions to this difficulty, Samsung Foundry applied Synopsys' Partial Layout Extraction (PLE) solution. PLE has the advantage of enabling post-layout simulation immediately during design by using a partially done layout DB. Which means that designer doesn’t need to wait for a full LVS/DRC clean layout DB, and designer can see the effect of parasitic and LDE on simulations while verifying the performance of the circuit during layout phase. Samsung Foundry completed the evaluation of PLE in collaboration with Synopsys using Samsung Foundry Advanced Node, which is expected to have a positive effect on reinforcement of Samsung Foundry Design Infrastructure.

As technology advances and circuit geometries become smaller wire interconnects become closer, thus, cross-coupling noise effects increase. To address issues resulting from crosstalk effects on circuit's functionality and performance, we propose the use of CCK check that analyses crosstalk noise in custom circuits. The CCK application checks the impact of the slow transitioning attacking "aggressors" neighbors on switching victims and measure the impact of the signal's transition time and overall delay pushout and report them on nets with coupling capacitors. It has demonstrated the capability of being efficiently used on any type/size circuits due to the fact that it has the capability of handling any number of nets in the design as victim nets are modelled separately. Thus, it helps isolate critical timing and functional paths or nets and allow the design to address the issues , hence fix any potential bugs in pre-silicon leading overall to faster-to-market and lower cost.

In a typical server or client SOC, a clock is distributed from a clock generator block (PLL) to multiple physical blocks that consume that clock for their internal flops. A lot of construction and analysis techniques are available to quickly identify the bottlenecks into CTS network however there is not much streamlined automation available to analyse global clock network from PLL to different physical blocks. Analysis of this clock network becomes important when you have very critical global buses and any skew component lost in global clock distribution could impact overall product performance. Hence early analysis and any data driven adjustment to global clock networks becomes important to forecast any global timing convergence issues early in design cycle.

Synopsys custom design platform with PrimeWave reliability environment and Custom Compiler features the industry’s first complete end-to-end (full lifecycle) unified reliability workflow. It covers early parasitic exploration & analysis, circuit checks (ERC), In-design analysis with signoff engines, analog fault simulation, electromigration and IR drop analysis, MOS self-heating and aging. This tutorial will cover several aspects of the platform-based reliability solutions available for the designers with the emphasis on new PrimeSim EMIR flow. In this flow we will highlight the simulator agnostic EMIR module with easy-to-use setup, analysis, and debug. This new EMIR solution greatly improves designers’ productivity by enabling existing PrimeSim users to access and deploy foundry certified reliability analysis technology with minimum ramp up effort.

With design trends in advanced nodes, designers need the comprehensive electrical analysis for the performance and reliability of integrated circuits. In the traditional design flow, designers perform electrical analysis near the end of the design cycle. However, with increasing design complexity and congestion, fixing EM issues at the end of the design process requires more time and can be costly. The in-design EM flow can be the solution for reducing or eliminating design iterations. In this session, we will present an overview of the steps in Synopsys Custom Compiler’s in-design electrical reporting process based on industry’s golden standard signoff tools – StarRC for parasitic RC extraction and PrimeSim RA for EM analysis. Additionally, we will introduce the results of in-design EM reporting process for Samsung advanced nodes.

The need for high spectral efficiency, lower energy consumption, and smaller footprint has given rise to the immense interest in using photonic integration in the data center interconnects. The pluggable’s are expected to decline over the years giving rise to the wide deployment of photonic integration and co-packaged optics. Just like the mature electronic-design automation (EDA) ecosystem, the commercial success of the photonic integrated circuits (PIC) rests on the maturity of the photonic process design kits (PDKs), and on a scalable and efficient photonic design environment. Photonics and electronics are vastly different, and yet an AMS-like schematic-driven layout (SDL) and simulation is a must to keep photonic design accessible to traditional electronic chip designers. In this paper, we present a PIC design methodology using GF 45SPLCO iPDK in Synopsys OptoCompiler Platform.

The growing need for multi-gigabit bandwidth system in Internet of Things (IoT) platforms has created the requirement of the SerDes PHY to operate across multiple dynamic temperature and voltage ranges. While BMODs (Behavioral MODels) of analog circuits provide a relative functional model for validating the closed loop features, actual performance of the circuits to the dynamic analog components such as temperature and voltage can only be verified through a mixed signal simulation with spice replacement. Here we explore and suggests methods that could be adopted by different IP's to dynamically change the simulation configuration and presents the results of how this method was adopted to verify the dynamic temperature range of a sub-block in a mixed signal environment. We also show how the same method could be extended and used to increase simulation performance and accuracy at various points in the mixed signal simulation.

Advance variation concepts are discussed. Also, we introduce sigma amplification technique which is used to validate the robustness of larger and medium size circuits. Running Monte Carlo Sigma Amplification using PrimeSim Continuum would present variability analysis with accuracy “ moderate sigma” and shorted runtime than conventional Monte Carlo where full-sampled runs are usually done. Thus, comparative analysis between conventional techniques and Sigma Amplification made and proved viability and robustness of Sigma Amplification techniques.

Growing design complexity coupled with advances in semiconductor process technology require more simulations to be run at higher accuracy levels on larger designs. The latest version of PrimeSim added support for the Ampere A100 GPU for further performance improvement. The PrimeSim Circuit Simulator was evaluated to measure performance gains with the A100 GPU using Samsung Foundry Advanced Node, compared to the previous PrimeSim evaluation where Samsung and Synopsys collaborated on using the V100 GPU. This presentation details the various cases used and the performance data obtained with the latest version of PrimeSim. Through this improvement, Synopsys PrimeSim Circuit Simulator with support for A100 GPU is expected to enhance Samsung Foundry design infrastructure.

As SoCs become larger and more complex and with a continuous drive to reduce currents in active or standby modes, there’s a need to not just simulate for functional correctness but also to quickly detect the leakage during every simulation at full SoC level, be it at full SPICE or mixed signal. Designers want to probe and analyze important currents to efficiently improve their designs. The second part of this problem is to track the leakage current to find its source with least manual efforts, and navigate the design hierarchy, linking the top nets with cells and current contributors.

To address this challenge, we have developed a tool called Iways which is intended for all SoC verification engineers and analog mixed signal designers. This tool creates 1) Probes for simulation 2) Post-processes output plot files and provides information on leakage currents 3) Helps point to the source of the leakage. This solution works with PrimeSim XA and VCS PrimeSim AMS flows used by our design teams. The solution supports for AoT (Analog-on-top) and DoT (Digital-on-top) netlists.

Iways tool works in 2 phases. In phase 1, probes for critical nets are generated automatically by intelligent detection of Device under Test. In Phase 2, Iways extracts average currents for probes generated in Phase 1.

The purpose is to reduce human intervention in probe generation for huge circuit designs. The user can control the generation of probes by specifying constraints to Iways in terms of depth, cell name, net name etc. For instance, user may choose to exclude certain cells from probe generation. Iways will treat these cells as grey box and will only generate probes if there is a short resistance through this cell. User can completely exclude this cell by specifying it as a blackbox, removing any visibility to short resistances in such cells.

The advantage of Iways is that the designer now doesn’t have to worry about creating his or her own supply probes. With only few constraints provided to Iways, user can reduce the number of probes and in turn the size of waveform file simplifying the analysis. Another advantage of this flow is the generated excel report. This file shows the design hierarchy and the significant contributors to the high leakage current values, pinpointing the designer to the exact violation area.

In this session, Astera Labs will present their recent experiences designing their purpose-built connectivity solutions for data-centric systems using Synopsys products in a public cloud environment. The flexible combination of Synopsys products and the cloud - with quick ramp up to scale and compute-for-burst options - expertly addressed resource limitations, thereby improving turn-around-time and ultimately reducing time-to-market for Astera's products. The presentation will include best practices and lessons learned.

You have been shifting compute workloads to the cloud for a while now, but are you seeing the full benefit of its flexibility and power? EDA in the cloud offers the ability to scale flexibly while improving quality of results, time to results, and cost of results. This session will talk about unleashing the cloud’s full potential.

Semiconductor development encompasses a variety of design and verification steps. Each of these steps employ specific tools and algorithms. These algorithms make use of different aspects of a microprocessor’s architecture. Synopsys VCS functional verification solution is the premier logic simulator and is one of the most heavily used products in the digital design cycle. AMD’s recently launched Milan-X processor features architectural elements that complement logic simulation and improve the performance of VCS. We will discuss how these microprocessor architectural features combined with the system level architecture of the Microsoft Azure HBv3 hardware-enabled cloud environment affects logic simulation and the advantages these features bring to logic simulation.

In this session, we will introduce and demonstrate a full RTL to signoff digital design flow in the cloud environment. This cloud-based digital design solution drives an RTL design through logic synthesis, physical implementation, and signoff without requiring to setup individual tools. Attend this session and see a live demo showing the Synopsys digital design solution in the Cloud.

Design and manufacturing complexities in market segments such as AI, 5G, Automotive and HPC pose significant challenge for physical verification engineers to achieve on-time design closure. An optimal blend of EDA tools and infrastructure optimization is required to enable maximum benefits and fastest time-to-market. IC Validator is focused on delivering continuous innovations in scalable performance with its latest technology advancements and ML-driven algorithms for fast convergence. Combining that with just-in-time infrastructure capabilities, leveraging cloud computing through collaboration with Amazon Web Services, designers get the best of both worlds of EDA+cloud synergies to meet their diverse complex challenges skillfully. Join us to hear insights on the IC Validator’s latest technology innovations together with AWS, including best practices and engineering takeaways for immediate project impact considerations.

This presentation is also included in the Physical Verification Track.

AI and ML (Machine Learning) are being used in many industries, and semiconductor design is no exception. Synopsys is leading the way with its DSO.ai solution which makes semiconductor design easier, faster, and achieve better performance. With increase in chip size and complexity, demand for HW resources required for semiconductor design is higher, and AI-driven solutions are accelerating this need further. This presentation will highlight best practices for applying AI-driven EDA solution in the cloud leveraging Synopsys’ DSO.ai on SAFE-CDP(Cloud Design Platform) which is the ready-to-use cloud based virtual chip design environment from Samsung. It will also provide suggestions for optimal use by comparing results of various cloud usage model, cloud architecture and scheduler setting in SAFE-CDP for improving efficiency with DSO.ai and better user experience. 

Library characterization is a highly-parallelizable, compute-heavy workload. Migrating it to the cloud requires large and frequent data transfers, using large amounts of dynamic compute resources efficiently, and mapping to on-prem user behavior. We present our experiences and solutions to bridge the gap: a high-throughput copy method, multiple job scheduling methods, and custom infrastructure.

Recent technical advances, scaling and growing innovation in cloud have accelerated the adoption of cloud computing in semiconductor design. Information security is paramount to this adoption. Engaging with cloud service providers (CSP) comes with a shared responsibility, where the CSP is responsible for security of the cloud and tenants are responsible for security in the cloud. In this presentation, we will present Synopsys' Defense in Depth Cloud Security approach and a share a Synopsys cloud case study.

SPICE-level verification is limited for each design team by the availability of compute resources and cost of EDA tools across the design cycle. The current business model leaves a simulator either idle in early design stages or at very high demand before tapeout. These inconveniences in timesharing of resources when combined with the need of powerful infrastructure to cater to compute-intensive simulation of hyperconvergent designs impose a productivity bottleneck. The PrimeSim Continuum simulation solution is now available on the cloud utilizing powerful cloud infrastructure which can run intensive simulations and streamlining the demand peaks using pay per use model. This cloud infrastructure includes GPU support which delivers 10x speedup compared to CPUs.

One of the most attractive uses of the cloud for chip development is bursting VCS workloads. VCS workloads scale very effectively and bursting to the cloud allows customers to leverage the huge scale of compute that the cloud offers. While hosting design data completely on the cloud is simpler and more efficient, many customers require full control and governance of their data in wholly owned storage. We will discuss a method customers can use to store their data on a wholly owned Pure Storage FlashBlade device located in an Equinix data center and connect to the Azure cloud for compute. This discussion will cover the architecture and performance of this implementation.

Design-technology co-optimization(DTCO) is one of key technologies to keep scaling down chip area in advanced process nodes. One of challenging tasks in DTCO is to secure of the sufficient amount of routing resource under the shrinking the routing resource and increasing complexity of design rule condition. In this work, we propose several design methodologies to overcome the severe design constraints in advanced node such as minimizing the routing usage by using the direct pin connection method with the various pin location. Our experiment demonstrates that additional area scaling can be achieved through the industrial test-cases using the proposed methods.

Along with the improvement of process technologies continues to advance, standard cell routability or pin accessibility become the major concerns which can effect design PPA and schedule. Further, for increasing of the advanced design rules, the various multiple height or area reduction of standard cell become more challenge. Although there are analytical-based approaches presented to check the cell routability and verify the layout-style. However, the integration test of routability is still needed to confirm in the PnR environment, it takes lots of time and can’t even simulate the whole cases in place and route. In this paper, we propose a simulation base approach to find out the router friendly cells for the design implementation under all possible place and route conditions. Experimental results show our approach can reduce 28% short violations in a real project. We divide the library routability problem into several independent target cells and conquer the run time issue in a reasonable run time. Our approach is one time effort for the target process then the result can be applied on the related designs.

Besides commonly used features of RTLA – logic restructuring, exploration and quick synthesis to assess PPA, another key value of using RTLA in early design pathfinding, is dirty data handling of incomplete RTL and DFT constraints. Immature RTL causes PPA related issues, Errors in DFT signal specifications results in longer runtimes to test DRC, and often incorrect DRC errors. In collaborative efforts among Synopsys and Intel PSG group, we architected a work-model to enable Front End RTL owners to flush through RTL, SDC, UPF and Scan related issues using integrated tool capabilities of RTLA and TestMAX Advisor. The paper tabulates PPA results, DFT constraint analysis and results and at the same time, compares QoR against typically used Fusion Compiler flow out of backend designs.

Silicon Design has become competitive in recent years. Every player demonstrates their success based on the aggressive Power, Performance, Area (PPA) and schedule targets met. One such area where all these vectors are clearly visible is constructing an optimal clock tree based on the architectural needs that result in the best PPA and runtime. Traditionally, tools try to balance the skew or meet the specified target latency/skew. For certain clocks such as source synchronous clocks or forwarded clocks, neither the skew nor latency are significant. In such cases, clock and data flow concurrently in the same direction or against each other. Currently, there is no dedicated solution out of the box for synthesizing such clocks. The default Clock Tree Synthesis results in a less optimal clock tree where more than required routing resources and clock devices are taken up resulting in higher clock area and higher runtime. On the other hand, a custom approach using clock tree planner can be adopted at the cost of more manhours and possible schedule delays. More often designers come up with a custom recipe for their design which are not portable across the designs and are not scalable. Therefore, a simple and generic technique is designed wherein a clock spine is constructed algorithmically and tapping sinks at the appropriate spine repeater mimicking a forwarded clock. The algorithm is parameterizable to control the locality and extent of the spine buffers. This has resulted in improved Power, Performance, and Area with a quick turnaround time. The algorithm is portable and scalable across designs and is process agnostic.

In a typical server or client SOC, a clock is distributed from a clock generator block (PLL) to multiple physical blocks that consume that clock for their internal flops. A lot of construction and analysis techniques are available to quickly identify the bottlenecks into CTS network however there is not much streamlined automation available to analyse global clock network from PLL to different physical blocks. Analysis of this clock network becomes important when you have very critical global buses and any skew component lost in global clock distribution could impact overall product performance. Hence early analysis and any data driven adjustment to global clock networks becomes important to forecast any global timing convergence issues early in design cycle.

With shrinking technology nodes and higher demand for Power, Performance, and Area (PPA) physical design is getting further complex. Time to market remains key in thorough execution. Multiple challenges are posed with low power architecture combined with increased transistors count per partition. This presentation proposes a systematic approach to physical design for TSMC N6 node using Synopsys Fusion Compiler advance capabilities. This presentation presents challenges with 30K ports, 1000s of feedthroughs, over 10 voltage domains, rectiliner floorplan , with about 50 secondary Power grid regions design including 2 million cell instances and ~2GHz max_freq. Various optimum methods with Fusion Compiler capabilities chalks out a holistic approach for such complex design.

FPlab is a novel approach for the creation of the inputs required for the floorplan flow, using parametrized model that reduces the manual edits for designers.

The industry trend is to increase logic and memory densities while enabling quicker integration with technology advancement and high-performance metrics. High speed designs are challenging designers to find efficient automation techniques to achieve high quality designs. Traditionally Metal-Insulator-Metal Capacitor (MIMCAP) planning and generation has been done at top level assembly design and at a slow pace to satisfy design requirements of reliability, density, and robustness. A way to modify and finetune top metal patterns and planning to improve MIMCAP with a quick turnaround is becoming vital for smooth product closures. We will propose a methodology to efficiently plan and automate top metal generation for power grid shapes along with MIMCAP optimization. We will show the planning for MIMCAP plates, top metal shapes, automated shape insertion and MIMCAP plates results tuning. Some of the layout challenges which we will be sharing, comprise of different voltage area requirements, special blockages, and custom regions with a different metal pattern to analyze before insertion of shapes for efficient integration and minimal layout clean-up effort.

The algorithms to convert from Binary-to-Gray codes and Gray-to-Binary codes are not new. The first times I documented these algorithms were in SNUG papers that I presented 20 years ago[1] and 19 years ago[2], and I had learned the these techniques from other senior engineers earlier in my career. Despite the fact that these algorithms have been around for decades, I still find RTL designers who do not know the algorithms and who expend great effort to implement the algorithms using large, tedious and error-prone case statements. The purpose of this paper is to document these important techniques using SystemVerilog with a title that will make it easier to discover through internet searches. The paper will also show SystemVerilog parameterized versions of these algorithms and will describe the use of the XOR gate as a programmable inverter.

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. In this tutorial, we will cover a full-flow voltage optimization and closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.

Complete ASIC Low Power Methodology overview from Architecture to signoff

Key Component that’s essential for Power Analysis are Representative Vectors. Irrespective of how accurate signoff-based power analysis tools are if vectors are wrong, results will be meaningless. Goal of this session is to talk about how Emulator based vectors can be used for accurate SoC level average , peak power analysis and what are the costs involved in getting the right vectors out of Emulator.

Power Analysis for long running Use Cases has been a challenge in pre-silicon domain. Power estimation tools in the industry were mostly written to consume shorter simulation based vectors. With the popularity of emulation, in the industry, designers are now able to emulate real world scenarios unto few seconds in pre-silicon time frame, But consuming these emulation based vectors in power estimation tools “efficiently” can still be challenge.

Another challenge in this power puzzle is accuracy of power estimated at RTL stage, even with good representative vectors, the RTL power results simply don’t match up with netlist based power analysis, mostly owing to inferior quality of underlying synthesis and power engines used in the traditional tools.

In this presentation, I will put forward the new methodologies we are using to successfully tackle both these challenges using the latest PrimePower feature sets.

The presentation will demonstrate a methodology and technique to optimize the leakage power of power switches (PFET) which are crucial in today’s nanometer process technology nodes to save total power of modern Integrated Circuits. It discusses automated power switch selection and replacement, to lower leakage variation based on both Static and Dynamic IR-drop margins across the power switches. This ensures the overall IR-drop still meets the power budget after optimization. The determination of preset threshold target of IR-drop through the power switches is the key to realistic optimization, without jeopardizing the overall chip level IR-drop of the design. A leakage saving of ~40% from this power switches optimization method for a project will be presented. It also contains a comprehensive run report that provides clear statistical evidence of total power savings achieved, and the number of power switches swapping for each variant that was done..

Current power flows look at individual registers or register bits when calculating clock gating efficiencies and highlighting wasted captures.  However, they do not consider the global impact of strengthening a register enable at the RTL module level across all instantiations of the register in a design. We have addressed this with a parser which uses Prime Power clock gating efficiency and power reports as inputs. This parser computes average clock gating efficiency metrics for all occurrences of a given register instantiated from a single RTL module and also their cumulative wasted power. The report sorts the RTL register definitions by cumulative wasted power in order to prioritize any clock gating enable improvements, or in other words, it identifies which RTL modules will yield the highest potential power savings across the entire design if their register enable condition is strengthened. This flow has been further extended to identify the design hierarchies with the highest potential power savings and also to understand expected chip level power savings from clock gating related fixes.

Selecting best standard cell library for Power Performance Area (PPA) is key to meeting product KPI. At ISO process nodes, transistor offering and standard cell layout architecture (height, poly pitch, M0/M1 pitch, fins-per-transistor, Vt, Lg etc.) availability of rich functional feature set is key to differentiated low power outcome for RTL Soft-IP implementation. This work defines a novel, vendor agnostic and automated method of measuring comparative functional standard cell library richness and its effect on improved PPA at the structural design block level. It describes a standard framework for design-of-experiment methodology and automated measurement of block level PPA impact due to unique feature set from vendor libraries along with a set of physical (cell area, transistor count, switching capacitance, Cdyn) and logical parameters (Boolean compaction ratio as improved logic composition) of the design that are computed in automated way to correlate back to measured library richness.

One of the biggest problems with RTL power estimation is accuracy comparing against sign-off power. If the estimation is not accurate, designers loss confidence in the tool. There are multiple factors that
make power estimation at the RTL level challenging. This presentation covers in details on the steps involved in addressing these challenges.

This presentation aims at discussing the impact of power globally and how every nanowatts matters in maintaining a green world. 

Ever advancing silicon technology is impacting physical design. Design rules are increasing 50-70% since 65nm process node and the complexity of Physical Verification (PV) checks is also exploding. Goal is to maintain ~ 24 hour Turnaround Time(ToT) for Full Chip PV. In this presentation we will present PV challenges arising from capacity, performance and QoR. We will see how Marvell collaborated with Synopsys to use unique features in IC Validator/ IC Workbench to achieve a ToT of 24-36 hours for a full cycle of PV checking for a reticle size switch chip using a combination of Cloud and on-premise Hardware.

Ever increasing design size and complex technology requirements for our advanced process node designs are driving the demand for highly productive and convergent physical verification flows. There is also greater need for huge computing power to meet tight time-to-market requirements. This presentation demonstrates Astera Labs’  IC Validator based physical signoff methodology to address the physical verification challenges and on-time design closure. We will discuss various technology areas, including PERC for reliability verification, Elastic CPU for optimal resource usage, efficient debugging with waiver flow and scalable full chip verification. We will also share best practices for using IC Validator on Amazon Web Services cloud.

Applications such as datacom, sensing, autonomous driving, and computing are driving demand for silicon photonics technology. For such Photonic Integrated Circuit (PIC) designs, both layout synthesis and physical verification demand innovative solutions to address unique challenges. For simulation and layout synthesis the Process Design Kit (PDK) should include accurate modeling of the active and passive devices as well as rapid synthesis capabilities so PIC designers can rapidly iterate to an optimum design. Once the layout is synthesized such non-traditional structures as “Curved lines / edges”, “Free angled edges” and “Acute angle corners” result in many false errors with traditional Design Rule Checking (DRC), and debug becomes difficult. On the other hand, there is concern about missing real errors with simplified screening algorithms. Additionally, optical devices provide a unique challenge for Layout Versus Schematic (LVS) verification related to wave-guide shapes and co-existence of electrical and optical pins. In this talk, we’ll present how these challenges are being addressed in an open foundry OptoCompiler PDK for design and simulation and the IC Validator platform for DRC and LVS, and are enabling PICs for a wide variety of applications.

Manufacturing complexities 5nm and below are driving the need for a faster, convergent and high productivity physical verification solution. IC Validator continues to deliver innovations in scalable performance, high productivity and robust debugging.  In this presentation, learn about latest IC Validator technology for physical verification productivity and performance and how to use these technologies in your design flow.

Design and manufacturing complexities in market segments such as AI, 5G, Automotive and HPC pose significant challenge for physical verification engineers to achieve on-time design closure. An optimal blend of EDA tools and infrastructure optimization is required to enable maximum benefits and fastest time-to-market. IC Validator is focused on delivering continuous innovations in scalable performance with its latest technology advancements and Machine Learning driven for fast convergence. Combining that with just-in-time infrastructure capabilities, leveraging cloud computing through collaboration with Amazon Web Services, designers get the best of both worlds of EDA+cloud synergies to meet their diverse complex challenges skillfully. Join us to hear insights on the IC Validator’s latest technology innovations together with AWS, including best practices and engineering takeaways for immediate project impact considerations.

Physical verification engineers are facing increased complexity in debugging advanced node designs due to sophisticated layouts and complex foundry design rules. IC Validator offers a robust set of debugging tools to help designers quickly debug and fix issues. In this tutorial, learn how to use IC Validator debugging features for a variety of physical verification flows, including DRC, LVS, Explorer, Voltage dependant rules and more. Also learn about latest debugging tools such as Dashboard and new VUE features that help in smart debugging and improve productivity.

Designing Photonics IC circuits presents a unique set of challenges for physical verification in the design flow. PIC design layout contains components that require smooth curves to operate efficiently. In this tutorial, learn about IC Validator technology for DRC and LVS verification to address the challenges for Photonics Integrated Circuits. We will cover new techniques in IC Validator to reliably verify the unique layout and design styles of Silicon Photonics designs, greatly reducing design time and improving tape-out confidence.

IBM’s Server team designs high performance processors for Z and P systems chips. Synopsys Design Services and AE teams have collaborated with IBM’s integration team to deploy LVS Explorer for fast Physical Design Verification (PDV) of IBM’s chip. This presentation will discuss the benefits that IBM observed of the deployment of LVS Explorer during a recent tape-out, as well as the process needed to setup LVS Explorer.

On the one hand, modern computer systems are becoming faster, more efficient, and increasingly interconnected with each generation. Thus, these platforms grow more complex, with new features continually introducing the possibility of new bugs. A growing number of increasingly sophisticated attacks are starting to leverage cross-layer bugs, thereby undermining the security of the entire system. On the other hand, globalization of the hardware supply chain has led to security and trust issues, especially in protecting the intellectual property (IP) cores against reverse engineering, piracy, and overbuilding.

In this talk, we explore the “hide and seek” approach followed by the Secure and Trustworthy Hardware (SETH) lab at Texas A&M University using Synopsys tools and design methodologies. In the “hide” episode, we explain how to hide the “secret sauce” of the design using Synopsys tools. In the “seek” episode, we detail how to find hardware vulnerabilities in modern processors using Synopsys tools. This talk will also feature the new challenges in this exciting area of hardware security research.

Hybrid and Series Turbo Electrified Aircraft architectures have their benefits with respect to fuel burn and CO2 emission reduction. Raytheon Technologies is working with DOE ARPA-E to develop next generation of electric propulsion system based on superconducting motor , its motor drive and a cryocooler.

In a series turbo-electric system, multi-MW class turbo-generators generate the electric power which is then distributed to various electric propulsion motors and their drives.  Such an electrical system is heavy as it produces a lot of heat which must be rejected to the ambient. Now, Carbon Neutral Liquid Fuels especially cryo-fuels such as Bio-LNG (liquid form at 120K) and Liquid Hydrogen (liquid at 20K) offer a formidable heat sink before the fuel is combusted in a turbo-generator to generate electricity.  Using cryo-fuel as a heatsink the power density and efficiency of the electric drivetrain can be drastically improved over state of the art. In this ARPA-E program, the fully superconducting motor (2.5MW) is operating at 20K while the motor drive (2.5MW) is operating at 120K. This approach yields very high power density and efficiency of the drive train components (>12.5kW/kg and >93% respectively – goals set by ARPA-E to take on the 20MW electrified aircraft grand challenge).

The presentation will focus on gaps in modeling methods of the power train at cryogenic temperatures (20K to 120K) and physics of power semiconductor devices that needs to be captured for accurate performance predictions to corelate with the experimental data.

Security has been very important aspect in software for some time to ensure hackers don’t get access to malicious attack. Hardware security is also emerging as very important aspect for hardware design because if underlying hardware platform is not secure then impossible to plug that in software alone. Microelectronics threat surface spans the entire lifecycle; from Architecture, design & verification, fabrication and assembly, deployment and operation; and attacker can find vulnerability anywhere in software and hardware stack. Hence comprehensive solution for security is required, starting from designing secure software to design and verification of security semiconductors with security IPs to enhance security.

Synopsys offers comprehensive security solution that the method, process, and technology to develop semiconductors and systems. Synopsys has vision to create comprehensive solution which makes security as a critical element of semiconductor  development, covering all areas of development : Architecture exploration, software development, design and verification of silicon which maps to a standard semiconductor cycle. In this presentation we will present this overall security vision, and the solutions which fits into that overall vision.

At the 2021 DARPA Electronics Resurgence Initiative (ERI) Summit and MTO Symposium, plans for the next iteration, named ERI 2.0, were discussed. One of the areas DARPA is planning to pursue is manufacturing complex 3D microsystems. The R&D needed for advanced microelectronics manufacturing would include the design, assembly, testing, and digital emulation of 3DHI microsystems, with an emphasis on: a) Multi-chip, multi-technology assembly and packaging; b) Tools for design, simulation, and test; c) Security; d) 3DHI (3-dimensional heterogeneous integration) interconnects; and e) Thermal management and power delivery. This presentation will focus on some of the challenges related to manufacturing complex 3D microsystems.

Seeing a need to automate the creation of secured silicon, even in untrusted environments, Synopsys is the prime contractor for the DARPA AISS (Automated Implementation of Secure Silicon) program. This session will review the Zero Trust design assumptions and potential threat vectors that this program addresses. Synopsys is using this program to accelerate the study of electronic security issues and develop mitigations that can be added to semiconductor chips with the ease of DFT insertion. We will review the security tool flow, delve into the proposed architecture, and expound upon some of the features already available for securing your next silicon device.

Modern SoC design and fabrication have become more complex over the years and establishing security and trust is quite a challenging task. Synopsys and FICS team from University of Florida have been working together on developing tools and methodologies to protect intellectual property (IP) cores, establish secure SoC design process, assess efficacy of the solutions, and ensure the design is fabricated and test securely in an untrusted foundry environment. This talk will provide a high-level overview of the challenges and some of the solutions being developed collaboratively. 

In the era of IoT, data security and privacy are an essential concern for communication between the large number of ubiquitous edge devices and the Internet backbone. Side-channel leakage analysis (SCLA) is one of the most critical data security vulnerabilities exploiting a variety of physical emissions from contemporary semiconductor ICs. As compromised ICs cannot be altered in the field, it is essential to verify side-channel countermeasures in the pre-silicon design stage, calling for actions from EDA industry. In this talk, we will introduce the breakthrough technology in Ansys’ multiphysics simulation platform to address IC design and security verification targeting side-channel leakage vulnerabilities.

Designing a solid architecture with security in mind requires extensive technical breadth and depth, especially when trying to shift design and verification teams’ mindsets. Determining what the security in a design is separates success from failure. After defining security to its basic essence, this talk will describe four design representations proven to be effective in security evaluations.

Accuracy in parasitic extraction is crucial for pre-silicon verification of SoC designs in advanced finfet nodes, sensitive foundational IP, and process variation. Transistor and local interconnect scaling in 3-dimensions results in exponential complexity to tune conventional model-fit extraction solutions. An accurate 3D field solver enables capacitance sensitive IP to achieve tighter silicon correlation. This paper discusses Intel’s first production library extraction using industry standard 3D field solver on 4nm technology. Runtime and accuracy trade-offs were evaluated, computation resource requirement and field solver convergence were identified. 10X accuracy over model-fit was achieved using high-capacity 3D field solver without impacting product schedules.

Cell functional verification is critical to standard cell library design. NVIDIA traditionally opted for binary vector-based functional verification, since verification and characterization can those vectors. But chip design trends toward lower power dissipation while improving performance, and manufacturing at advanced nodes, led to exploration of formal methods to logically verify cell libraries.

Accurate Aging-Aware Robustness with Machine-Learning Speed-up Modeling circuit performance degradation due to transistor aging has a been a long-standing challenge in STA. Highly sensitive to stress condition and signal activity, the aging effect can vary significantly due to different operating conditions. It is extremely expensive to account for all possible aging conditions during cell characterization. As a result, aging effect has been treated with derate-based methodology, which often becomes overly pessimistic or lacks signoff coverage. This presentation will showcase an innovative solution that delivers high signoff accuracy to avoid pessimism related to derate-based solution. Combining advanced delay modeling techniques with machine learning, the novel approach is capable of performing accurate scaling across a wide range of aging conditions with low runtime overhead. The presentation will also demonstrate a fully-automated flow that performs path-level aging HSPICE simulations for rigorous accuracy validation.

Accuracy in parasitic extraction is crucial for pre-silicon verification of SoC designs in advanced finFET nodes, sensitive foundational IP, and process variation. Transistor and local interconnect scaling in 3-dimensions results in exponential complexity to tune conventional model-fit extraction solutions. An accurate 3D field solver enables capacitance sensitive IP to achieve tighter silicon correlation. This presentation discusses Intel’s first production library extraction using industry-standard 3D field solver on 4nm technology. Runtime and accuracy trade-offs were evaluated, computation resource requirement and field solver convergence were identified. 10X accuracy over model-fit was achieved using high-capacity 3D field solver without impacting product schedules.

As technology scales and Machine Learning designs get more complex, the STA challenge continues to explode. Design size, PPA goals and the number of modes and PVT corners, make the runtime for flat STA increasingly challenging. Cerebras Wafer Scale Engine™ required a more scalable solution for their next-gen designs, that could provide better productivity and shorten the time to STA signoff.

In this session, learn how PrimeTime HyperGrid enables orders of magnitude better TAT/memory and compute resources, achieving overnight full-chip flat distributed STA, while guaranteeing accuracy. Cerebras designers can efficiently and effectively perform timing analysis on our multi-billion instance designs with 100% QoR-match, and complete design runs overnight which was not feasible in previous flat runs. HyperGrid achieves the holy grail of superior scalability and 100% QoR-match with its unique, highly efficient partitioning and load balancing. It’s logic-cone based partitioning is block size independent and models SI effects accurately.

This paper discusses IR aware STA that allows including the effects of IR-drop up to a certain limit into STA runs to study the impact on timing and allows waiving mechanism if there is a timing margin. IR aware STA also provides the capability of translating IR-drop violations into timing violations and fix these timing violations using timing ECO flow up to certain limit beyond IR-drop budget.

As advanced technology nodes increase in process complexity, power integrity challenges continue to grow as the shrinking of wire-width leads to higher resistances which impacts IR drop. Identifying and fixing dynamic IR drop is time consuming and is traditionally addressed early in the design flow as the general perception that late-stage dynamic voltage drop fixes could impact chip timing and this leads to more design ECO iterations. This paper will cover the integrated RedHawk-SC/Tweaker ECO flow which performs surgical fixes on targeted areas and complete fast interactive what-if loops, to improve power integrity and deliver superior last-mile PPA closure.

It is primal to get very fast ECO turnaround time at advanced nodes to meet the aggressive design tapeout schedules. Design teams are under constant pressure to meet the aggressive tapeout schedules and, therefore signoff with a much shorter ECO closure cycle time, even though the designs metrics of scenarios and instances are reaching greater than 100+ and over two hundred million, respectively. Every ECO change can potentially become a bottleneck and influence the tape-out schedule. Tweaker’s Gigachip hierarchical ECO flow provides different ways to handle the hierarchical designs to reduce the runtime without impacting the fix rate. This session will discuss Tweaker’s Gigachip hierarchical ECO flow, which we have used in our current implementation flow.

This paper describes some options to properly constrain the asynchronous timing paths of synchronization logic which pass both data and clock from one clock domain to another clock domain.

As we march towards advanced nodes of 3nm and below – the demands on library characterization are multiplying. We have a come a long way from simple LUT based NLDM/NLPM modeling for timing and power for library cells. Characterization now fundamentally has to include – current based timing/power/noise models, variation aware models, aging and reliability models. And of course with the stress of shorter TAT’s (turn around time) and much larger scale of corners and conditions – with little or no compromise on accuracy targets. An accurately characterized library is a fundamental unit in a design and hence the signoff quality expectations are very high. Achieving these goals within the shortest possible TAT is a challenge faced by characterization tools and flows all around.

Synopsys’ SiliconSmart is a characterization solution for standard cells, IO’s and memories. It is architected with an embedded golden reference SPICE engine and produces signoff quality libraries. With its unique placement and proximity to PrimeTime and HSPICE – SiliconSmart produces Libs with results that correlate-by-construction in PrimeTime® Static Timing Analysis (STA).

SiliconSmart tackles this daunting task of characterization at various levels of Usability, Functionality, Accuracy and Performance. With a strong collaboration between TSMC and Synopsys, SiliconSmart library characterization solution has been certified on latest process technologies to provide our mutual customers with high confidence of achieving signoff accuracy and faster time-to-market through an accelerated path for TSMC N3, N4 and N5-based designs.

In this presentation we will showcase how the long standing collaboration is providing significant benefits to our mutual customers.

The increasing parasitic challenges at advanced nodes impacts the time to accurate design closure. Synopsys and Samsung collaborate closely on addressing the most advanced nodes parasitic modeling challenges to deliver accurate results with scalable runtime and high capacity of core extraction and field solver technologies. Improving QOR, TAT & designer productivity while providing golden signoff extraction are the key aspects driving StarRC product roadmap. This session will provide an overview of our current technologies, innovation in adv. Nanosheets/GAA processes, solving the process modeling challenges, and new features for digital design flow & integration with digital platforms.

Timing closure has traditionally used a fixed margin for IR-Drop . This usually leads to over-design as the margin is typically calculated to cover the worst case. On the flip side, if the margin is not close to the worst case, there is potential to miss out on some real timing paths. To ensure that Timing closure is focusing on real timing critical path it is most accurate to back-annotate voltage values to cells in design with actual IR drop as seen in EMIR analysis. This is the approach discussed in this paper using the “read_dvd” & voltage scaling features of PrimeTime.

Transistors manufactured with different threshold voltage (Vth) have different timing characteristics. Transistors within the same Vth class are highly correlated, while between Vth classes are less so. Today’s techniques of applying min/max derates to account for the variation is pessimistic, therefore forcing designers to design clock trees with a single Vth class which is overly restrictive. Qualcomm has used its own solution to add additional corners which focus timing derate on only 1 the dominant Vth class in mixed Vt clock tree designs, ensuring the derates are applied consistently in launch & capture paths. In this presentation, we will discuss how Qualcomm evaluated Synopsys’ Vt-skew which addresses the problem by enumerating the possible Vth combination across launch & capture, finds the worst case combination and makes the assignment. By adopting the feature, Qualcomm is able to reduce the number of corners required for signoff and no longer has to maintain their internal scripted solution.

At lower technology nodes (N7 & below), a design’s robustness against variation-effects has been a growing concern. Traditional methods that rely on margining has proved effective only at the cost of sacrificing PPA. To successfully compete in the market with lower manufacturing costs, companies need to design reliable products operating at the highest performance and lowest power possible. In this presentaiton, we will discuss how PrimeShield’s Design Variation Analysis, helped in modeling the impact of variation accurately on our N7 high-performance block and delivered a 11MHz of frequency boost by identifying bottleneck cells impacting performance and improved design’s robustness (JSR) by nearly 80%. The paper also discusses how we saved power using Voltage Slack & Robustness analysis features on a low-power design by providing voltage slack gain of 20mV without sacrificing performance while ensuring the IR robustness of the design.

Timing closure in hierarchical designs are challenging in terms of runtime and memory because of the large size of the design. It adds more complexity when there are a lot of multi-instantiated modules (MIM) as the tool needs to check the margin and violation across all the instantiations of design. Also, for power ECO, the runtime will take longer if power recovery is run for both interface and internal logic as tool must work on all positive node logic. In this presentation, we will demonstrate the multiple technologies in Tweaker ECO available to reduce TAT for large designs.

A methodology is needed to validate the Hybrid StarQTF Flow. With foundry provided files we will present a methodology that can be used on critical cells ahead of actual foundry qualification for the hybrid StarQTF extraction flow using QuickCap NX. The biggest advantage is to allow for design work to proceed when PDK components are available on day 1 rather than delay by 3-6 weeks for official qualification. In the process, we will also show how one can use StarRC Parasitics Explorer interface seamlessly to do output netlist checks to catch potential issues upfront as well as do detailed parasitics analysis to make better design decisions.

Register File designs have traditionally been analyzed with NanoTime. The margin checks required were added manually in the NanoTime flow. However, larger and more complex multi-port designs have limitations with this methodology as there is excessive runtime and memory consumption, in addition to being tedious and error prone. NanoTime Memory Register File Feature automates the analysis of such Register file designs. This paper explores the setup of NanoTime Memory Register File flow and also discusses the margin checks which are executed automatically. Results of Accuracy correlation between NTM flow and SPICE simulation will also be discussed.

 This paper discusses the problem of how to constrain the asynchronous timing paths inside the asynchronous FIFO design. Because of the limitation of the STA tool, to properly and efficiently constrain the asynchronous timing paths, some workaround and practices are proposed.

The lifecycle management of silicon products is changing how SoC design and semiconductor test communities think about device and system performance, health, and predictability. There is a growing opportunity for meaningful data to be analyzed at each lifecycle stage. Providing insight across the design, manufacturing, test, and in-field deployment phases plays a critical role in improving resilience and reliability while also shortening time to market. Furthermore, once systems are deployed in the field, analytics can be conducted on large sample data sets across entire product ranges or fleets, providing visibility of long- term trends that can guide power and performance optimizations. The nexus of test within silicon lifecycle management is an exciting development area and will create significant value and growth in the coming years.

Design teams are constantly in need of new technologies to minimize test time and test data volume, accelerate design-for-test (DFT) development, and ensure optimal design implementation. In this tutorial, we will provide guidance on using two key TestMAX technologies that address these challenges: DFTMAX SEQ codec which encompasses flexible sequential compression to significantly reduce test data volume for large designs; and Streaming Fabric which is a high-throughput bus-based data delivery structure with a standardized to reduce test time while easing its physical imeplementation. In addition, key runtime improvements for ATPG will also be covered..

AI/ML accelerators are typically massive with billions of gates, highly parallel architecture with thousands of replicated processing units and large amounts of distributed memory. The size and complexity along with the adoption of cutting-edge technologies for AI architectures present a significant challenge to defining an efficient DFT and test strategy. In this tutorial, we start with describing the features of typical AI chips from DFT perspective and key factors to be considered when defining an efficient test architecture. Next, we discuss the current DFT approaches and their challenges in terms of test metrics and implementation. Finally, we present the next generation of scalable and flexible scan test-bus and test-setup solutions that are ideal for AI designs and address these challenges to meet and exceed their test goals.

Artificial Intelligence (AI) or Machine Learning (ML) systems are being deployed in almost all the application. For these systems to be practical, they must process large amounts of data very quickly. Semiconductor companies are design dedicated AI chips to meet the processing requirements of these applications. As the design sizes and complexity of these AI designs continue to increase, the efforts involved in DFT, pattern generation and testing has also increased exponentially. This requires detailed and careful planning and implementation of test architecture to meet the test goals and minimize test costs. In this presentation, Esperanto will show the DFT flow, test strategy and trade-offs for their large ET-SoC-1 ML chip which has over one thousand cores and large distributed on-chip SRAM with limited number of test pins while minimizing DFT logic area.

The growing market for automobiles, consumer electronics, communication products and servers has increased the demand for system on chips. This renders a faster turnaround time of the design cycle from architecture to manufacture testing and ensuring the chips are defect free. For decades, design for testability (DFT) techniques have been used and integrated at the gate level of the design to test the manufactured chips efficiently. The only caveat of implementing the DFT at the gate level of the design is the detection of any design issues during ATPG or after synthesis is done, which would cause additional churns of synthesis cycles to fix the problem and in turn impact the overall turnaround time of the product cycle.

In this presentation, we will describe how TestMAX Advisor’s connectivity checks came was helpful to verify the pipeline stages and point-to-point signal connections in SARC’s designs early in the design flow. We will give an overview of the issue its potential impact on time to market. We will also review the initial flows as well as the current updated flow which incorporates TestMAX Advisor and how it aided us to detect and fix issues in our designs quickly and easily. We will summarize results of Advisor checks and how it helped us detect improper pipeline stages and how these checks helped monitored connectivity correctness throughout the design cycle. Concluding our experience in a single statement: TestMAX Advisor easily helped in detection and early visibility of the problem, which helped us improve our time to market and made usage, debugging, fixing easy to the users in various design stages.

Memory Built-In Self-Test (MBIST) architectural design and implementation, in addition to a successful Failure Analysis (FA) methodology, pose significant technical challenges for modern highly integrated SoCs. Functional requirements such as clocking, power, layout and routing can heavily influence architectural considerations, and there is a critical need for effective failure mapping mechanisms to assist the FA and Fault Isolation (FI) process. SoCs for AI applications typically consist of thousands of embedded memories that perform complex computations. DFT strategies developed for such products must heavily consider post-silicon requirements that aim to assist production yield analysis and recovery. This paper describes an automated MBIST and Logical-to-Physical (L2P) mapping methodology implemented for Intel VPU products, developed in coordination with FA/FI engineering teams.

Today’s SoC’s have many mission critical applications which require a very low defective-parts-per-million (DPPM) metric. There are two ways to guarantee low DPPM - Continuous testing and monitoring of semiconductor devices throughout their lifecycle and increased test coverage. Ever increasing design size, gate density and new fault models further increase the amount of test data and test times. With pressure to reduce the number of pins on the SOC, it is challenging to meet test time and cost goals. High-speed functional interfaces such as PCIe and USB can double duty as high speed test access interfaces addressing above mentioned challenges. In this presentation, we will cover design implementation considerations and verification strategies for an innovative solution that leverages existing functional protocol-based high speed interfaces for structural testing and provides a consistent portable method to test silicon throughout its lifecycle.

Electronic Wafer Maps creation and transfer between production sites are very essential to daily manufacturing operations of Ampleon. We are relying on Silicondash to generate, merge, analyze, control and export wafer maps at different test stages. It starts with the Automated Visual Inspection (AVI) defect maps from the Wafer Diffusion Fabrication, followed by the creation of the prober and post-inking maps during electrical wafer test process then finally to the Automated Optical Inspection (AOI) wafer map of Pre-Assembly process. Final consolidated wafer map is then exported under the specific format that will serve as input data for the assy plant to pick only the good dice for subsequent steps. Throughout the years of using Silicondash and in partnership with Synopsys, series of projects related to wafer map flow and post-inking tools have been developed that support the automation roadmap of the factory.

Synopsys Yield Explorer (YE) has been used extensively by the Embedded Processing (EP) team at TI to drive COGS improvements (yield at entitlement) in our deep submicron foundry engagements. This paper will demonstrate how YE has been successfully utilized not only with our Foundry partners but also by our internal Fabs at TI. YE has been instrumental in supporting identification of systematic yield loss and also as an aid to identify sources of baseline yield loss in both memory and digital logic blocks of EP and Analog mixed-signal devices.

This presentation will explain details on a joint Synopsys / Advantest solution for HSIO SCAN test through USB or PCIe on the V93000 production ATE. Devices enabled with the supporting DFT can use the new Link Scale digital instrument on the V93000 for high-throughput SCAN test in volume manufacturing.

Modern ICs and their applications employ numerous tunable parameters that can have a significant effect on performance. These parameters can be tuned at design time (e.g. cache sizes), in design bingup (e.g. compiler flags, OS settings) or even in the field by the customers. The large number of these parameters makes it almost impossible to deliver near-optimal designs using reasonable manual efforts. In this talk, the concepts of AI-powered static and dynamic real-time tuning will be presented. In addition, we will demo how SiliconMax Optimizer applies these concepts to address use-cases like design-space exploration and outperforming the competition with benchmark optimization.

Advanced node technologies now underpin the capabilities offered by the latest cutting-edge technologies. The demand for greater performance and functionality has in turn brought about new silicon and system challenges associated with the physical management of these complex, high gate density advanced node architectures. There are enormous benefits to having greater visibility and insight into the operational margins within a chip. At small technology nodes the process variations between devices and across the die increases. In addition aging is becoming a major reliability issue as wire resistance and transistor characteristics change over time and effect timing margins. In-field performance optimization is only possible if you can have fine grain observability of the state of the device non-intrusively while in mission mode. You need to know how far you can lower the vim and maintain proper throughput. You need to know temperature gradient across the die to manage performance per power domain precisely. Path Margin Monitor provides this level of observability and is a key enablers to take performance per watt curve to the next level. Once captured, this margin data can be fed into a central hub for either edge analytics or cloud analytics. The analytics can then explore operational limits for speed, and particularly voltage, as if you know how low you can push your supply levels down you have a great mechanism for supply and therefore power optimization.

Recent growth in utilizing artificial intelligence and data centers have led to an explosion in the use of emerging memories, from embedded FinFET SRAMs, CAMs, and MRAMs in SOCs; to off-chip HBM and DDR DRAMs in chiplets and 3DIC packages. This tutorial will first present the resiliency challenges of such emerging memories throughout their lifecycle, and then will discuss optimizing the health of such emerging memories using the Synopsys TestMAX SMS solution, which is typically used for managing all the silicon lifecycle stages: from silicon debug in early bring up stage to shorten the time-to-market; to self-test and repair during volume production stage to improve quality and yield; to power-on self-test in the field to address aging defects; to in-system periodic checking in the field to improve functional safety; and finally to fault tolerance and error correction during the mission mode to address a range of transient errors. All of the above are realized by on-chip and off-chip data analytics.

This panel will discuss the emerging paradigm shift towards Silicon Lifecycle Management and how it is changing the way the Semiconductor Test and SoC communities think about device and system performance, health and predictability. The new era of SLM has opened up opportunities for developing new, insightful sensing and analytics technologies that are now providing solutions to the optimization challenges faced by test teams, chip and system developers across a wide range of applications. Silicon Lifecycle Management is one of the most exciting areas of evolution for the semiconductor industry and based on the value it brings to each phase of the device lifecycle from early design right through to in-field. As Silicon Lifecycle Management continues to gain momentum it is just a matter of time before adopting and using SLM is standard procedure on every project.

The semiconductor industry for high-performance computing (HPC) is aware of the increasing amounts of complex data in the data center that must be processed with minimum latency and maximum power efficiency. However, other trends and use cases have evolved that add to the design complexity of HPC SoCs. New AI accelerators for a more hyper convergent compute platform, data processing units or NICs as independent infrastructure endpoints, new data center optics from pluggable to near-package to co-packaged for shorter interconnects between dies/chips, U.2/U.3 storage form factors for more standards-based SSDs, new network switches for higher bandwidth up to 51.2Tb, and many others are just a few of the trends that HPC SoC designers must keep up with. This presentation highlights today’s most relevant HPC trends and explains how such trends are driving the demand for faster standards-based interfaces including PCIe 5.0/6.0, 112G/224G Ethernet, CXL 2.0/3.0, USR/XSRSerDes and OpenHBI.

HBM2 and HBM2E have been meeting the requirements of high-performance computing, artificial intelligence and graphics SoCs up until now. However, due to the increase in data volume and compute, the required memory bandwidth is now exponentially higher. Earlier this year, JEDEC announced the HBM3 standard as an innovative approach with key attributes such as 6.4 Gb/s data rates, 64GB density, improved ECC features and better energy efficiency at lower operating voltage. This presentation describes the new features of HBM3, trending applications and new changes the standard is offering designers to meet their memory requirements.

PCIe 6.0 was just released in January 2022. There are many new features, such as 64GT/s data rate, PAM-4 signaling, FLIT (Flow control unit) encoding – including a whole new packet header format, L0p low-power state and more, that designers must now consider. The new PCIe 6.0 architecture will also enable many new and existing high-performance applications like AI accelerators, PCIe storage, 800G Ethernet, and re-timers. This presentation outlines the essential features of PCIe 6.0 and their impact on designs for mainstream and new applications. The presentation also highlights implementation considerations, including security, that SoC designers must be aware of when moving to PCIe 6.0 designs.

Since 2015 the semiconductor industry has seen a boon in AI processing. As the industry matures, we see innovative architectures tackle very complex cloud, on-premise, and edge applications. This requires more collaboration, drives software optimizations for specific hardware and pushes the limits of current bandwidth capabilities. Understanding what drives these systems and how to optimize is critical for next generation IP selection. It is the system that drives innovation and that system is made up of highly complex pieces all working together to accomplish a state of the art solution for AI.

Today's SoC and IPs are growing to be extremely complex which require more powerful emulation/prototyping methods to allow validation customers (hardware and software validation team) to shift-left their schedule and reduce bug escapes to end customers. Currently we deployed 3 main platforms in this arena, target-less big box emulators using transactors only, FPGA platforms with real devices, and companion platforms using emulator tool chain with FPGA platforms. Because of the different focus and targeted users, each of these platforms made different trade off during the process of converting SoC and IP RTL code into emulation models. We currently have separate teams of engineers delivering these models in parallel. This submission described our next-gen methodology on how to maximize the common reusable portion of the model to have a combined repository and build flow to generate different models. This improved the consistency between the emulation models and reduced the team size needed to generate multiple models for different validation customers.

NextGen SoCs with advanced graphics, computing, machine learning and artificial intelligence capabilities are posing new unseen challenges in verification signoff. It is important to reduce turnaround times and enable faster time-to-market. Emulation helps verify software scenarios and longer running validation tests which cannot be run in a simulation environment. The need of the hour is a fast emulator with full debug capabilities and also ensuring a high throughput. The Synopsys ZeBu emulator is the industry’s fastest emulator which ensures a “shift-left” in overall emulation signoff and at the same time ensures that no subtle bugs escape into silicon.

With increasing SoC complexity, growing design sizes and advanced graphics and computing architectures, early and efficient verification signoff is important to reduce turnaround times and enable faster time-to-market. Emulation platforms play a significant part in running long tests and verifying real world scenarios. A fast emulator with full debug capabilities is needed to achieve this. This paper will cover the details on the evaluation done for one of the designs at NXP using Synopsys ZeBu EP1, and discuss how it helped to achieve performance goals.

Open-source RISC-V cores are fully configurable processors, with an open-source instruction set, that are available in different configurations and are also highly customizable. One such is the RISC-V Pulpino microcontroller that has an ecosystem of integrated peripherals and associated bus circuitry to realize a RISC-V centric SoC. The ZeBu emulation platform is a standard emulator used for emulation of processors, SoCs and complex hardware IPs. This platform is used to emulate the Pulpino microcontroller SOC where the Pulpino core is ported on ZeBu hardware and it executes the programs as if on a RISC-V based SoC whereas its different peripherals interact with ZeBu transactors for connectivity and data transfer. This enables one to realize a full SOC emulation environment. The Silicon team at Accenture, aimed to build an environment with the intent of handling the various challenges of migrating a SystemVerilog Verification environment to a ZeBu based emulation environment. The team built the emulation environment grounds-up and applied changes to reach a fully working state.

Access to an Emulators for a small-scale project could be feasible, only when the solution eliminates the hefty cost of Emulator ownership. Synopsys Cloud4 ZeBu Emulator fulfilled this need. Synopsys Cloud4 ZeBu, is cloud based emulation solution to achieve validation for IP and SoCs. It is supported with a library of transactors for many common interfaces and comes with strong debug features.

Simulation of the ZeBu Emulation setup, is a key stage in the process. The ZeBu Simulation environment eased the development of the Cpp testbench and in having a running setup in place before going to the ZeBu Emulation hardware. This drastically reduce the time spent on ZeBu Hardware and allowed tighter iteration cycles. The transactors support debug messages, and configurable debug level. Along with transactor message, the trace generation using file I/O feature, ztdb waveform dump, and display messages could be used to conveniently debug the design. The project also illustrates how a full SOC can be emulated, in the cloud and many of the components developed can be leveraged for a faster turn-around for full SOC emulation.

This session, co-presented with Arm, introduces the audience to the pre-silicon BSA compliance testing solution and presents real customer use cases around compliance and system performance verification. Synopsys Pre-Silicon BSA compliance testing solution, developed in collaboration with Arm as part of the SystemReady program, is the only solution in the market with built-in PCIe Sub-system performance verification and analysis. With various applications and solutions around Arm SoC, it is important to have a framework that helps you scale. The Arm SystemReady certification program aims to make sure that your software just works seamlessly across a vibrant, diverse ecosystem of hardware. Arm BSA compliance is a key requirement for SystemReady and all certification bands. System compliance testing is best suited during design and verification. Exercisers available in pre-silicon environments provide custom stimuli and additional compliance coverage. System Integration and hardware compliance issues are common leading to software visible defects and interoperability issues. Issue mitigation in software is costly, challenging, and not always feasible, requiring patches, and custom OS or FW workarounds for SystemReady which are costly to develop and maintain. Worst case scenario for mitigation may require silicon re-spin or risk non-adoption by customers.

Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. To conquer the verification challenge of complex SoCs, companies are shifting their development paradigm to a software first approach. By considering the target software up front as a critical part of the SoC development process, designs teams are able to signoff a new SoC for production with high confidence.

In this tutorial we will cover the primary pre-silicon methods, along with their benefits, to execute a software first strategy:

• Virtual prototyping
• Emulation
• FPGA-based prototyping

Through the example of a production processor design project, we will provide insight into each methodology and how it helps to accelerate verification coverage. This session is hosted by a software first methodology expert and aimed at verification and software teams working on next-generation SoC designs.

Verification complexity of memory systems has grown exponentially with memory devices and controllers design sizes increasing at each successive process node. Memory systems are difficult to validate until all the silicon components become available and integrated. Pre-silicon systems verification using simulation is slow with significant efforts in building the simulator environment. Hardware assisted emulation and validation is used to alleviate the limitation of simulation by utilizing transactor models for better performance.

This presentation presents the details of the Synopsys ZeBu emulation platform coupled with a host computer for validating pre-silicon memory systems by leveraging memory transactors for significant performance gain. Memory transactors, memory controllers, and testbench are synthesized into the Synopsys ZeBu emulation platform. The use of memory transactors solves the problem of sending/receiving pin data between the host computer and the emulation platform every single clock by using a transaction-level based protocol that contains wire-level communication within the hardware emulator. The memory transactors eliminate the interface bottleneck and maximize performance between the testbench in the hardware emulator and the test in the host computer. This Synopsys ZeBu emulation platform allows memory systems to be fully validated quickly before silicones become available.

Increased use of end-user streaming applications, cloud computing, and 5G deployments that require low-latency, high-throughput, and secure traffic are pushing the boundaries of network capacity. This demand drives the market for ultra-high-speed devices powered by state-of-the-art application-specific integrated circuit (ASIC) and system-on-a-chip (SoC) solutions.Increased use of end-user streaming applications, cloud computing, and 5G deployments that require low-latency, high-throughput, and secure traffic are pushing the boundaries of network capacity. This demand drives the market for ultra-high-speed devices powered by state-of-the-art application-specific integrated circuit (ASIC) and system-on-a-chip (SoC) solutions.Not having the right tools, knowledge, or methodology to robustly test the chip designs may cause costly, image-damaging re-spins that further delay time to market.IxVerify is the industry’s first test solution purpose-built for pre-silicon verification. With IxVerify, Keysight and Synopsys are leading the way in transforming the EDA market by offering virtualized design verification solutions that work in conjunction with next-generation verification flows—leveraging virtualization to reduce dedicated and specialized hardware costs while offering increased flexibility.Whether validating routing and switching or 5G designs, IxVerify enables new and improved test methodologies to simplify hardware design verification, fuels greater collaboration between hardware and software teams, and enables a shift-left approach to testing earlier in the product lifecycle.

Audience

Companies designing and testing ASIC/ SoC/ Chipset for:

- Routers or Switches

- SmartNICs

- Automotive networking 

- Optical transport

- 5G O-RU/O-DU

EdgeQ’s 5G solution unifies wireless connectivity and artificial intelligence in a singular open design paradigm. This next generation SoC is a conglomeration of multiple advanced subsystems and the IO subsystem consists of PCIe, Ethernet and eCPRI among others. With the multiple interfaces that come into play there is a need for early SW development targeting functionality across different areas. Also, it becomes important to validate the complex 5G Base-Station software stack in the system context as RTL matures.

In this paper, we discuss our experience in virtualizing all these different interfaces for an emulation setup including the debug interfaces like JTAG. Specifically for PCIe , we show how we leverage the Virtual Machine adaptor that enables the insertion of an emulated design as if it was physically connected to a host. The Virtual Machine adaptor makes the emulated design accessible to the host software and enables development of the full 5G base-station software stack. We are thus able to create a framework which allows early software development in the same environment where the software is to be used.

In addition, we will also highlight how we effectively ensured emulation readiness early for an effective utilization of the time on the Emulation Cloud .

We will share techniques used in integrating ZeBu transactors, validating connectivity and basic functionality on simulation platform, so that we can subsequently do a ‘slam dunk’ on the emulation platform on the cloud thus leveraging the time on the cloud. The paper also highlights the advantage of taking a modular approach for the bring up of a large 5G base-station SoC in improving the turnaround.

Usually, tremendous efforts are put into verifying every functional feature of a design using a well-organized and predictable stimulus. However, a design is bound to face adverse operating conditions due to human errors and changing environmental conditions. So, in addition to normal functionality, handling errors and invalid scenarios are indications of robustness, which is a major factor in improving product quality. The efficient testing of any design requires erroneous and illegal scenarios which can verify that the design can recover smoothly - either by handling them expectedly or by ignoring them. Hence, error injection becomes a crucial part of any testbench.

This paper will majorly focus on various aspects of error injection: what would be the best place to inject errors & how the testing can be implemented on random error scenarios. Then we will also examine the best error injection approach among “Sequence” and “Callbacks.” We have employed these in PCI-Express verification environment as a reusable solution. Effective error injection approach reduces the verification effort by 30-40% to discover hidden problems of design compared to directed and random testing.

I will describe my trial of the new VCS multi-cycle path verification capabilities. I tested this new verification tool against a high-speed design which includes hundreds of multi-cycle paths. I introduced errors into the design and constraints, and the tool successfully caught them.

Our design team has developed a fairly similar custom verification methodology, but it requires a lot of maintenance, and most other teams do not have anything similar. The VCS multi-cycle path verification is easy to use, and will add important coverage of multi-cycle path constraints. The VCS methodology is also more direct, in that it directly reads the multi-cycle constraints and tests them.

Large-scale SoC development involves running many EDA tools repeatedly on a design by multiple designers. This often results in completely duplicate or somewhat duplicate tool runs by various engineers in a team, leading to significant wastage of compute and human resources as well as causing unnecessary delay in project execution. In this presentation we plan to describe an end-to-end caching methodology that takes advantage of the caching capabilities in the modern EDA tools and allows sharing of EDA tool run results among the engineers of a large-scale RTL development team. We have achieved 50-70% runtime reduction in building our logic simulation models, while ensuring safe usage of cached content. In Section A, we will describe the specifics of the issue we address and what Synopsys technology we use. Section B will describe our caching methodology, and Section C will present the results from a server-class production design.

Testbench reuse to improve TTM is a constant challenge, ultimately leading to the advent of methodologies like UVM and Portable Stimulus. Can waveforms also be reused to improve verification efficiency and TTM?

Learn more about the latest Verdi offering – Intelligent Debug Accelerator (IDX), the next generation smart debug environment reuse with waveforms across different contexts like IP debug, testbench debug, and Assertion IP verification.

In today’s complex verification of ASIC/FPGA designs, verification teams are constantly looking for new ways to reduce verification cycles.

In this session we introduce Dynamic Test Load (DTL) in VCS to enable users to load tests dynamically at run time without re-generating the simulation database. The dynamically loaded tests yield significant savings in compile and runtime by avoiding rerunning of common verification patterns like reset and initialization sequences.

In addition to this, we will also delve into the recommended coding styles for test packages, uvm_phases, save points to achieve the maximum benefit from DTL. This will help setup your environment to dramatically improve verification productivity.

Intelligent Coverage Optimization (ICO) is designed to be used during all stages of testbench development. At the early stages, even before coverage is developed, learn how to use ICO effectively to gain testbench insights and to expose and triage testbench bugs, which in turn help write better constraints that are conducive to faster coverage convergence.

Modern verification environments have multiple agents with their own drivers and interfaces. Sometimes communication is required between the drivers, for example for reactive sequences that depend on the response from another driver. Techniques are presented to enable reactive sequences with cross agent/driver response using standard UVM methodology.

In this session we will cover how native integration between Execution Manager and ICO (Intelligent Coverage Optimization) in VCS can achieve faster and higher coverage using constraint biasing on the full regressions. Users can save on compute resources and improve regression TAT by running fewer graded tests.

It is widely known that UVM (and its predecessor OVM) has built-in phasing mechanism. UVM functionalities are staged with phases. UVM has predefined common phases (build, connect, end_of_elaboration, start_of_simulation, run, extract, check, report, and final). UVM also defines a set of task phases (reset, configure, main, shutdown, and corresponding pre_ and post_ phases), which can run in parallel with run phase. To many these are all they know about UVM phases while how UVM phasing mechanism works is still a mystery. Lack of in-depth understanding of UVM phasing mechanism often causes confusion, sometimes leads to unintended behavior (verification bugs) or inefficiency.

This paper tries to demystify UVM phasing mechanism. It discusses how UVM phases work in detail and explains key concepts such as phase, domain, and schedule. UVM phasing mechanism consists of at least two major parts: 1). constructing a Directed Acyclic Graph (DAG) of phases; 2). executing phases based on DAG.

The first part is important as it determines in which order phases are executed. Other than predefined common phases and UVM task phases, custom phases can be defined and inserted into DAG for execution. Furthermore, user can realign (sync) and unsync phases. This technique is especially useful for VIP intergration, which can have independent and potentially different phasing structure.

The second part is equally important if not more. After the construction of a test object, all UVM functionalities are executed through phases following DAG. UVM provides many hookups (callbacks) across phases. In order to use these callbacks efficiently it is essential to have a good understanding of phase execution.

Finally this paper talks about how to debug phase issues.

Specifying the low power (LP) intent of design in the UPF file is a manual, tedious process and does not always scale from one abstraction level to another or from one tool to another in the SoC design flow. Built on the Synopsys Verdi advanced debug platform, Verdi UPF Architect provides an automated flow to create and optimize the UPF from IP to SoC. Verdi UPF Architect facilitates a single golden power intent allowing the designer to generate UPF, meeting various tool requirements in the flow. Also learn how the generated UPF can be further optimized using the Synopsys VC LP static low power verification solution.

Lint became the generic term given to design verification tools that perform a RTL static analysis based on a series of rules and guidelines signaling good coding practices with common errors, resulting in catching buggy RTL problems early. When these rules are breached, Lint flags the potential bugs within the code for review by the design engineer. Typically, Lint tools are excellent for checking compliance relative to best coding practices but may lack the finesse to accommodate the subtle differences present across multiple in-house coding styles. This shortcoming has manifested lately with SoC designs becoming increasingly dependent on third-party IP with each IP using different coding styles.

This session covers best practices required to find the RTL bugs using VC SpyGlass Lint along with functional lint analysis using formal enabling significantly reduced noise.

Discover how VC SpyGlass RDC can be utilized for huge complex designs to gain 100% signoff confidence providing 3X or higher performance using multicore capability and noise reduction using skip-resetless flow.

System on Chip (SoC) designs generally consist of multiple modes to deliver desired configurability requiring CDC signoff for each mode individually. Executing CDC signoff for each mode manually is inefficient and involves duplication of efforts. Come and join this session to find out how VC SpyGlass CDC can help improve signoff efficiency for these designs.

In this tutorial, we will cover how RTL designers can perform PPA analysis early in the design cycle with 3X faster productivity. Built on the unified Fusion Data Model, RTL Architect provides fast physical aware feedback leveraging Synopsys' world-class implementation and golden signoff solutions to deliver results that correlate-by-construction. This compliments the flow with VC SpyGlass static verification methodology for early RTL signoff.

Discover how Low Power Connectivity Checking (LP CC) can be leveraged to formally verify connectivity specs for SoCs with complex low power schemes. By eliminating any error introduction during the implementation of connectivity specification within the protection logic, leveraging LP CC can ultimately lead to higher confidence in the added low power functionality.

Formal model checking is a powerful methodology to find corner-case bugs and save the verification resources. It utilizes mathematical techniques to verify the RTL design and the reference model. In this paper we will introduce a few applications of VC Formal coverage analyzer that can be used early on to shift left the coverage closure phase, and reduce the effort in a modern coverage-driven verification process.

Performance, power, area (PPA) optimized RTL signoff solution requirements are more intense than ever. Join this session to learn how VC Formal Sequential Equivalence Checking (SEQ) can help verify various PPA optimization strategies, like clock gating, retiming, microarchitecture changes. This includes on-the-fly machine learning enabled powerful formal engines, innovative technologies such as automatic check generation, intuitive Verdi debug and a comprehensive signoff methodology.

Efficiency is crucial when working with SystemVerilog RTL design and UVM Testbenches. Syntax mistakes, coding violations, and the resulting problems increase the daily stress of engineers. Synopsys Euclide solves many of these problems by providing seamless incremental code and lint checking during SystemVerilog code bring up for both design and testbench while providing valuable feedback, seamless code navigation and a powerful autocomplete capability.

Attend this session to discover several new Euclide features that are helpful when working with new workflows. This talk will also share ideas on how to structure your Euclide setup to get the best performance, tuned to the varying team requirements.